MPC9772FA データシートの表示（PDF） - Motorola => Freescale

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MPC9772FA

3.3V 1:12 LVCMOS PLL Clock Generator

Motorola => Freescale 

MPC9772 Individual Output Disable (Clock Stop) Circuitry

The individual clock stop (output enable) control of the

MPC9772 allows designers, under software control, to

implement power management into the clock distribution

design. A simple serial interface and a clock stop control logic

provides a mechanism through which the MPC9772 clock

outputs can be individually stopped in the logic ‘0' state: The

clock stop mechanism allows serial loading of a 12-bit serial

input register. This register contains one programmable clock

stop bit for 12 of the 14 output clocks. The QC0 and QFB

outputs cannot be stopped (disabled) with the serial port.

The user can program an output clock to stop (disable) by

writing logic ‘0' to the respective stop enable bit. Likewise, the

MPC9772

user may programmably enable an output clock by writing logic

‘1' to the respective enable bit. The clock stop logic enables or

disables clock outputs during the time when the output would be

in normally in logic low state, eliminating the possibility of short

or ‘runt' clock pulses.

The user can write to the serial input register through the

STOP_DATA input by supplying a logic ‘0' start bit followed

serially by 12 NRZ disable/enable bits. The period of each

STOP_DATA bit equals the period of the free-running

STOP_CLK signal. The STOP_DATA serial transmission

should be timed so the MPC9772 can sample each

STOP_DATA bit with the rising edge of the free-running

STOP_CLK signal. (See Figure 5.)

STOP_CLK

STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC

Figure 5. Clock Stop Circuit Programming

TIMING SOLUTIONS

9

MOTOROLA

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