RM5261A-250-H データシートの表示（PDF） - PMC-Sierra
部品番号
コンポーネント説明
メーカー
RM5261A-250-H Datasheet PDF : 42 Pages
| |||
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
3.11 System Control Co-processor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor. In the MIPS architecture, the system control co-processor (and thus the
kernel software) is implementation dependent.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual
memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5261A incorporates all system control co-processor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261A includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
Figure 4 CP0 Registers
PageMask
5*
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
Context
4*
Count
9*
BadVAddr
8*
Compare
11*
47
Status
Cause
12*
13*
Index
0*
EPC
14*
TLB
Random
1*
XContext
20*
(entries protected
from TLBWR)
0
Wired
6*
PRId
15*
ECC
26*
CacheErr
27*
ErrorEPC
30*
LLAddr
17*
TagLo
28*
TagHi
29*
Config
16*
* Register number
Used for memory
management
Used for exception
processing
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
16
Document ID: PMC-2002240, Issue 2
Share Link: 