RM5261A-350-H データシートの表示（PDF） - PMC-Sierra

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RM5261A-350-H

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet

Preliminary

3.13 Virtual to Physical Address Mapping

The RM5261A provides three modes of virtual addressing:

• user mode

• kernel mode

• supervisor mode

This mechanism allows system software to provide a secure environment for user processes. Bits

in the CP0 register Status determine which virtual addressing mode is used. In the user mode, the

RM5261A provides a single, uniform virtual address space of 1 TB (2 GB in 32-bit mode).

When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4

GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of

the virtual address.

The RM5261A processors also support a supervisor mode in which the virtual address space over

2 TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual

address.

When the RM5261A is configured as a 64-bit microprocessor, the virtual address space layout is

an upward compatible extension of the 32-bit virtual address space layout.

Figure 5 shows the address space layout for 32-bit operation

Figure 5 Kernel Mode Virtual Addressing (32-bit)

0xFFFFFFFF

0xE0000000

Kernel virtual address space

(kseg3)

Mapped, 0.5GB

0xDFFFFFFF

0xC0000000

Supervisor virtual address space

(ksseg)

Mapped, 0.5GB

0xBFFFFFFF

0xA0000000

Uncached kernel physical address space

(kseg1)

Unmapped, 0.5GB

0x9FFFFFFF

0x80000000

Cached kernel physical address space

(kseg0)

Unmapped, 0.5GB

0x7FFFFFFF User virtual address space

(kuseg)

Mapped, 2.0GB

0x00000000

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

17

Document ID: PMC-2002240, Issue 2

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