NJU6676CH データシートの表示（PDF） - Japan Radio Corporation
部品番号
コンポーネント説明
メーカー
NJU6676CH
Japan Radio Corporation
NJU6676CH Datasheet PDF : 46 Pages
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NJU6676
PRELIMINARY
3-4) Column address set
As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is
necessary to execute both “page address set” and “column address set” before accessing. The 8-bit
column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column
address register.
Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be
accessed, so that the DDRAM will be able to be continuously accessed without “column address set”
instruction.
The column address will stop increment and the page address will not be changed when the last
address (83)H is addressed.
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
0
1 A7 A6 A5 A4 Upper 4-bit
0 A3 A2 A1 A0 Lower 4-bit
A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
Column address
0
1
:
130
131
3-5) Status read
This instruction reads out the internal status regarding “busy flag”, “ADC select”, “display on/off ” and
“reset”.
A0 RD WR D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
BUSY
ADC On/Off RESET
0
0
0
0
BUSY : When D7 is “1”, the LSI is being busy and can’t accept any instructions.
ADC
: It shows the correspondence between the column address and segment drivers.
When D6 is “0”, the column address (131-n) corresponds to segment driver n.
When D6 is “1”, the column address (n) corresponds to segment driver n.
Please be careful that read out data is opposite of “ADC select” instruction data.
On/Off : It shows display on or off status.
When D5 is “0”, the LSI is in display-on status.
When D5 is “1”, the LSI is in display-off status.
Please be careful that read out data is opposite of “ADC select” instruction data.
RESET : It shows reset status.
When D4 is “0”, the LSI is in normal operation.
When D4 is “1”, the LSI is during reset operation.
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