MT41J128M データシートの表示（PDF） - Micron Technology

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MT41J128M

DDR3 SDRAM

Micron Technology 

Figure 120: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit

T0

T1

T2

Ta0

CK#

CK

CKE

COMMAND

tANPD

ODT A

asynchronous

DRAM RTT A

asynchronous

ODT B

asynchronous

or synchronous

RTT B

asynchronous

or synchronous

ODT C

synchronous

DRAM RTT C

synchronous

RTT,nom

tAOFPD (MIN)

tAOFPD (MAX)

RTT,nom

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tc0

Tc1

Tc2

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

tXPDLL

PDX transition period

ODTLoff + tAOF (MIN)

tAOFPD (MAX)

tAOFPD (MIN)

ODTLoff + tAOF (MAX)

RTT,nom

ODTLoff

Td0

Td1

NOP

NOP

tAOF (MAX)

tAOF (MIN)

Note: 1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.

Indicates break

in time scale

Transitioning

Don’t Care

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