HM5164165TT-6 データシートの表示（PDF） - Hitachi -> Renesas Electronics
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HM5164165TT-6 Datasheet PDF : 36 Pages
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HM5164165 Series, HM5165165 Series
Refresh (HM5165165 Series)
Parameter
Refresh period
Refresh period (L-version)
Symbol
t REF
t REF
Max
64
128
Unit
Note
ms
4096 cycles
ms
4096 cycles
Self Refresh Mode (L-version)
HM5164165L/HM5165165L
-5
-6
Parameter
Symbol Min Max Min Max Unit Notes
RAS pulse width (self refresh)
t RASS
100 —
100 —
µs
26
RAS precharge time (self refresh)
t RPS
90
—
110 —
ns
26
CAS hold time (self refresh)
t CHS
–50 —
–50 —
ns
30
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) t RAD + tAA (max).
11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) t RAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD
(min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15. tDS and tDH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16
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