HM5164165J-6 データシートの表示（PDF） - Hitachi -> Renesas Electronics

部品番号

コンポーネント説明

メーカー

HM5164165J-6

64M EDO DRAM (4-Mword × 16-bit) 8k refresh/4k refresh

Hitachi -> Renesas Electronics 

HM5164165 Series, HM5165165 Series

Notes concerning 2CAS control

Please do not separate the UCAS/LCAS operation timing intentionally. However skew between

UCAS/LCAS are allowed under the following conditions.

1. Each of the UCAS/LCAS should satisfy the timing specifications individually.

2. Different operation mode for upper/lower byte is not allowed; such as following.

RAS

UCAS

LCAS

Delayed write

Early write

WE

3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is

satisfied, EDO page mode can be performed.

RAS

UCAS

LCAS

t UL

4. Byte control operation by remaining UCAS or LCAS high is guaranteed.

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