CY7C4201(2010) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4201 Datasheet PDF : 20 Pages
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
WCLK
D0 –D8
FF
NO Write
tSKEW1[14]
tWFF
Figure 10. Full Flag Timing
NO Write
NO Write
tDS
tSKEW1[14]
DATA Write
tWFF
tWFF
DATA Write
WEN1
WEN2
(if applicable)
RCLK
REN1,
REN2
tENS
tENH
tENS
tENH
OE
Q0 –Q8
LOW
tA
DATA IN OUTPUT REGISTER
tA
DATA Read
WCLK
tCLKH
WEN1
Figure 11. Programmable Almost Empty Flag Timing
tCLKL
tENS tENH
NEXT DATA Read
WEN2
(if applicable)
PAE
RCLK
REN1,
REN2
tENS tENH
tSKEW2[21]
Note
22
tPAE
N + 1 WORDS
INFIFO
tENS
tENS tENH
Note
23
tPAE
Notes
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a read is performed on this rising edge of the read clock, there are Empty + (n – 1) words in the FIFO when PAE goes LOW.
Document #: 38-06016 Rev. *D
Page 14 of 20
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