MX23L6454 データシートの表示（PDF） - Macronix International

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MX23L6454

64M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface

Macronix International 

MX23L6454

Figure 4. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

S#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-Bit Address

D

23 22 21 3 2 1 0

MSB

High Impedance

Q

Data Out 1

Data Out 2

76543 2107

MSB

Note: 1. Address bits A23 is Don't Care.

Read Data Bytes (READ)

The device is first selected by driving Chip Select (S#) Low.

The instruction code for the Read Data Bytes (READ)

instruction is followed by a 3-byte address (A23-A0), each

bit being latched-in during the rising edge of Serial Clock

(C). Then the memory contents, at that address, is shifted

out on Serial Data Output (Q), each bit being shifted out, at

a maximum frequency fR, during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Figure 4. The first

byte addressed can be at any location. The address is

automatically incremented to the next higher address after

each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ)

instruction.When the highest address is reached, the

address counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by

driving Chip Select (S#) High. Chip Select (S#) can be

driven High at any time during data output.

P/N: PM1127

REV. 1.1, MAR. 09, 2005

7

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