MX25L1635DMI-12 データシートの表示（PDF） - Macronix International

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MX25L1635DMI-12

16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH

Macronix International 

MX25L1635D

(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write

Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR

instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as

shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write

Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0

(WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is

entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data

on SI-> CS# goes high. (see Figure 13)

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,

and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 6. Protection Modes

Mode

Status register condition

Software protection

mode(SPM)

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

bits can be changed

WP# and SRWD bit status

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Memory

The protected area cannot

be program or erase.

Hardware protection

mode (HPM)

The SRWD, BP0-BP3 of

status register bits cannot be

changed

WP#=0, SRWD bit=1

The protected area cannot

be program or erase.

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change

the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software

protected mode (SPM).

- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD,

BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode

(SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been

set. It is rejected to write the Status Register and not be executed.

P/N: PM1374

REV. 1.5, OCT. 01, 2008

17

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