NAND01G-A データシートの表示（PDF） - STMicroelectronics
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NAND01G-A
STMicroelectronics
NAND01G-A Datasheet PDF : 57 Pages
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
REVISION HISTORY
Table 29. Document Revision History
Date
Version
Revision Details
06-Jun-2003
1.0
First Issue
07-Aug-2003
2.0
Design Phase
27-Oct-2003
3.0
Engineering Phase
03-Dec-2003
Document promoted from Target Specification to Preliminary Data status.
4.0
VCC changed to VDD and ICC to IDD.
Title of Table 2.. changed to “Product Description” and Page Program Typical Timing
for NANDXXXR3A devices corrected. Table 1., Product List, inserted on page 2.
13-Apr-2004
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.
Figure 19., Cache Program Operation, modified and note 2 modified. Note removed
for tWLWH timing in Table 20., AC Characteristics for Command, Address, Data Input.
Meaning of tBLBH4 modified, partly replaced by tWHBH1 and tWHRL min for 3V devices
modified in Table 21., AC Characteristics for Operations.
References removed from RELATED DOCUMENTATION section and reference
5.0
made to ST Website instead.
Figure 6., Figure 7., Figure 29. and Figure 32. modified. Read Electronic Signature
paragraph clarified and Figure 28., Read Electronic Signature AC Waveform,
modified. Note 2 to Figure 30., Read C Operation, One Page AC Waveform, removed.
Note 3 to Table 7., Address Insertion, x16 Devices removed. Only 00h Pointer
operations are valid before a Cache Program operation. IDD4 removed from Table
18., DC Characteristics, 1.8V Devices. Note added to Figure 32., Block Erase AC
Waveform. Small text changes.
28-May-2004
TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die
6.0
devices added. Figure 19., Cache Program Operation modified.
Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch
(1Gbit Dual Die devices) in Table 28., Ordering Information Scheme.
02-Jul-2004
Cache Program removed from document. TFBGA55 package specifications added
(Figure 40., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package
7.0
Outline and Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch,
Package Mechanical Data).
Test conditions modified for VOL and VOH parameters in Table 19., DC Characteristics,
3V Devices.
01-Oct-2004
Third part number corrected in Table 1., Product List. 512 Mbit Dual Die information
added to Table 10., Copy Back Program Addresses. Block Erase last address cycle
8.0
modified. Definition of a Bad Block modified in Bad Block Management paragraph.
RoHS COMPLIANCE added to SUMMARY DESCRIPTION. Figure 3., Logic Block
Diagram modified.
Document promoted from Preliminary Data to Full Datasheet status.
03-Dec-2004
Automatic Page 0 Read at Power-Up option no longer available.
9.0
PC Demo board with simulation software removed from list of available development
tools. Chip Enable (E) paragraph clarified.
13-Dec-2004
10.0
Rref parameter added to Table 16., Operating and AC Measurement Conditions.
Description of the family clarified in the SUMMARY DESCRIPTION section.
25-Feb-2005
WSOP48 replaced with USOP48 package,
11.0
VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm) package,
TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm) package.
Changes to Table 21., Table 18. and Table 2.
56/57
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