NCP1395 データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

NCP1395

High Performance Resonant Mode Controller

ON Semiconductor 

NCP1395A/B

Deadtime Control

Deadtime control is an absolute necessity when the

half−bridge configuration comes to play. The deadtime

technique consists of inserting a period during which both

high and low side switches are off. Of course, the deadtime

amount differs depending on the switching frequency,

Vdd

Icharge:

Fsw min + Fsw max

+

−

Idis

hence the ability to adjust it on this controller. The option

ranges between 150 ns and 1.0 ms. The deadtime is actually

made by controlling the oscillator discharge current.

Figure 41 portrays a simplified VCO circuit based on

Figure 33.

S

DQ

Clk Q

R

Ct

+ 3 V−1 V

Vref

DT

RDT

A

B

Figure 41. Deadtime Generation

During the discharge time, the clock comparator is high

and unvalidates the AND gates: both outputs are low. When

the comparator goes back to the high level, during the

timing capacitor Ct recharge time, A and B outputs are

validated. By connecting a resistor RDT to ground, it

creates a current whose image serves to discharge the Ct

capacitor: we control the deadtime. The typical range

evolves between 150 ns (RDT = 30 kW) and 1.0 ms (RDT

= 600 kW). Figure 44 shows the typical waveforms

obtained on the output.

Soft−Start Sequence

In resonant controllers, a soft−start is needed to avoid

suddenly applying the full current into the resonating

circuit. In this controller, a soft−start capacitor connects to

pin 4 and offers a smooth frequency variation upon startup:

when the circuit starts to pulse, the VCO is pushed to the

maximum switching frequency imposed by pin 2. Then, it

linearly decreases its frequency toward the minimum

frequency selected by a resistor on pin 1. Of course,

practically, the feedback loop is suppose to take over the

VCO lead as soon as the output voltage has reached the

target. If not, then the minimum switching frequency is

reached and a fault is detected on the feedback pin

(typically below 600 mV). Figure 43 depicts a typical

frequency evolution with soft−start.

http://onsemi.com

18

Share Link: