NCP1253 データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

NCP1253

Current-Mode PWM Controller for Off-line Power Supplies

ON Semiconductor 

NCP1253

solves this potential issue by adding an extra capacitor on the

auxiliary winding. However, this component is separated

from the VCC pin via a simple diode. You therefore have the

ability to grow this capacitor as you need to ensure the

self−supply of the controller without jeopardizing the

start−up time and standby power.

Triggering the SCR

The latched−state of the NCP1253 is maintained via an

internal thyristor (SCR). When the voltage on the Vcc pin

exceeds the internal latch voltage, the SCR is fired and

immediately stops the output pulses. When this happens, all

pulses are stopped and VCC is discharged to a fix level of 7 V

typically: the circuit is latched and the converter no longer

delivers pulses. To maintain the latched−state, a permanent

current must be injected in the part. If too low of a current,

the part de−latches and the converter resumes operation.

This current is characterized to 32 mA as a minimum but we

recommend including a design margin and select a value

around 60 mA. The test is to latch the part and reduce the

input voltage until it de−latches. If you de−latch at Vin =

70 Vrms for a minimum voltage of 85 Vrms, you are fine. If

it precociously recovers, you will have to increase the

start−up current, unfortunately to the detriment of standby

power.

The most sensitive configuration is actually that of the

half−wave connection proposed in Figure 25. As the current

disappears 5 ms for a 10 ms period (50 Hz input source), the

latch can potentially open at low line. If you really reduce the

start−up current for a low standby power design, you must

ensure enough current in the SCR in case of a faulty event.

An alternate connection to the above is shown below

(Figure 26):

In this case, the current is no longer made of 5 ms “holes”

and the part can be maintained at a low input voltage.

Experiments show that these 2 MW resistor help to maintain

the latch down to less than 50 Vrms, giving an excellent

design margin. Standby power with this approach was also

improved compared to Figure 25 solution. Please note that

these resistors also ensure the discharge of the X2−capacitor

up to a 0.47 mF type.

The de−latch of the SCR occurs when the injected current

in the VCC pin falls below the minimum stated in the

data−sheet (32 mA at room temp).

Frequency Foldback

The reduction of no−load standby power associated with

the need for improving the efficiency, requires a change in

the traditional fixed−frequency type of operation. This

controller implements a switching frequency foldback when

the feedback voltage passes below a certain level, Vfold, set

around 1.5 V. At this point, the oscillator enters frequency

foldback and reduces its switching frequency. The peak

current setpoint is following the feedback pin until its level

reaches 1.05 V. Below this value, the peak current freezes to

Vfold/4.2 (250 mV or 31% of the maximum 0.8−V setpoint)

and the only way to further reduce the transmitted power is

to diminish the operating frequency down to 26 kHz. This

value is reached at a feedback voltage level of 350 mV

typically. Below this point, if the output power continues to

decrease, the part enters skip cycle for the best noise−free

performance in no−load conditions. depicts the adopted

scheme for the part.

1 Meg

1 Meg

N

Vcc

L1

Figure 26. The Full−wave Connection Ensures Latch

Current Continuity as well as a X2−Discharge Path.

http://onsemi.com

12

Share Link: