NCP3163BPWG データシートの表示（PDF） - ON Semiconductor

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NCP3163BPWG

3.4 A, Step-Up/Down/Inverting 50-300 kHz Switching Regulator

ON Semiconductor 

NCP3163, NCV3163

MAXIMUM RATINGS (Note 1)

Rating

Symbol

Value

Unit

Power Supply Voltage

Switch Collector Voltage Range

Switch Emitter Voltage Range

Switch Collector to Emitter Voltage

Switch Current

Driver Collector Voltage (Pin 8)

Driver Collector Current (Pin 8)

Bootstrap Input Current Range

Current Sense Input Voltage Range

Feedback and Timing Capacitor Input Voltage Range

Low Voltage Indicator Output Voltage Range

Low Voltage Indicator Output Sink Current

Power Dissipation and Thermal Characteristics

VCC

0 to +40

V

VCSW

−1.0 to +40

V

VESW

−2.0 to +40

V

VCESW

+40

V

ISW

3.4

A

VCC

−1.0 to +40

V

ICC

150

mA

IBST

−100 to +100

mA

VIPKSNS

(VCC − 7.0) to (VCC + 1.0)

V

Vin

−1.0 to +7.0

V

VCLVI

−1.0 to +40

V

ICLVI

10

mA

Thermal Characteristics

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Air

RqJC

RqJA

°C/W

15

56

Storage Temperature Range

Tstg

−65 to +150

°C

Maximum Junction Temperature

TJmax

+150

°C

Operating Ambient Temperature (Note 3)

NCP3163

NCP3163B

NCV3163

TA

°C

0 to +70

−40 to +85

−40 to +125

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per MIL−STD−883, Method 3015.

Machine Model Method 200 V.

Charged Device Model 750 V for corner pins and 500 V for others (according to AEC−Q100).

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded.

4. The pins which are not defined may not be loaded by external signals.

PIN CONNECTIONS

1

LVI Output

2

Voltage Feedback 2

3

Voltage Feedback 1

4

GND

5

N/C

6

Timing Capacitor

7

VCC

8

Ipk Sense

(Top View)

16

Bootstrap Input

15

Timing Capacitor 1

14

Switch

Emitter

13

12 N/C

N/C 2

VCC

3

Ipk Sense

4

Driver Collector 5

11

Switch Collector 6

10 Switch Collector

Switch Collector

7

9

Driver Collector

Switch Collector 8

Switch Collector 9

GND

EP Flag

18 GND

17 Voltage Feedback 1

16 Voltage Feedback 2

15 LVI Output

14 Bootstrap Input

13 Switch Emitter

12 Switch Emitter

11 Switch Emitter

10 Switch Emitter

Note: Pin 18 must be tied to EP Flag on PCB

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