AD9802 データシートの表示（PDF） - Analog Devices

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AD9802

CCD Signal Processor For Electronic Cameras

Analog Devices 

AD9802

The disadvantage of this circuit is that the control voltage will

AD9801/AD9802 EVALUATION BOARD DESCRIPTION

be supply dependent. If additional precision is required, an

Power Supply Connectors

external op amp can be used to amplify the VREFT (1.75 V) or J1 VDD: +3 V supply for the AD9801/AD9802. Data

VREFB (1.25 V) pins on the AD9802 to the desired voltage

sheet specifications are given for +3.15 V. Operational

level. These reference voltages are stable over the operating

range is from +3 V to +3.5 V.

supply range of the AD9802. Low power, low cost, rail-to-rail

J2 AVCC: +5 V supply for the AD8047 buffer, and for the

output amplifiers like the AD820, OP150 and OP196 are speci-

PGACONT and PIN potentiometers. If the buffer am-

fied for 3 V operation. Alternatively, a precision voltage refer-

plifier is not needed, AVCC may be connected to the

ence may be used. The REF193 from Analog Devices features

VDD supply.

low power, low dropout performance, maintaining a 3 V output

with a minimum 3.1 V supply when lightly loaded.

J3 AVSS: –5 V supply for the AD8047 buffer. If the buffer

amplifier is not needed, AVSS may be connected to J4.

Power and Grounding Recommendations

The AD9802 should be treated as an analog component when

J4 AGND: This is the analog ground plane for the

OBSOLETE used in a system. The same power supply and ground plane

should be used for all of the pins. In a two-ground system, this

requires that the digital supply pins be decoupled to the analog

ground plane and the digital ground pins be connected to ana-

log ground for best noise performance. If any pins on the

AD9802 are connected to the system digital ground, then noise

can capacitively couple inside the AD9802 (through package

and die parasitics) from the digital circuitry to the analog

circuitry. Separate digital supplies can be used, particularly if

slightly different driver supplies are needed, but the digital

power pins should still be decoupled to the same point as the

digital ground pins (analog ground plane). If the AD9802 digi-

tal outputs need to drive a bus or substantial load, a buffer

should be used at the AD9802’s outputs, with the buffer refer-

enced to system digital ground. In some cases, when system

digital noise is not substantial, it is acceptable to split the

ground pins on the AD9802 to separate analog and digital

AD9801/AD9802 and the buffer amplifier. The two

ground planes are already connected together in one

place on the evaluation board.

J5 DGND: This is the digital ground plane for the

LVXC3245 transceivers. The two ground planes are

already connected together in one place on the evalua-

tion board.

J6 +3D: +3 V digital supply for the LVXC3245 transceivers.

J7 +3/5D: +3 V or +5 V digital supply for the LVXC3245

transceivers. This voltage determines the logic compat-

ibility of the evaluation board. If 3 V clock levels and

3 V digital output levels are to be used, connect +3 V to

J7. If +5 V clock levels and +5 digital output levels are

to be used, connect +5 V to J7.

Input Connectors

J8 DIN: Unbuffered input to the AD9801/AD9802. This

ground planes. If this is done, be sure to connect the ground

input is 50 Ω terminated by R4, which may be removed

pins together at the AD9802.

if no termination is required. See Input Configurations

To further improve performance, isolating the driver supply

for more information.

DRVDD from DVDD with a ferrite bead can help reduce kick- J9

back effects during major code transitions. Alternatively, the use

of damping resistors on the digital outputs will reduce the out-

put rise times, reducing the kickback effect.

VIN: Input to the AD8047 buffer amplifier. This

input is 50 Ω terminated by R5, which may be re-

moved if no termination is required. This op amp

can be used as a buffer to drive the DIN pin on the

Evaluation Board

An evaluation board for the AD9802 is available. The board

includes circuitry for manual PGA gain adjustment, input signal

AD9801/AD9802, or as a buffer for driving the direct

ADC input on the AD9802. See Input Configurations

and the AD9802 data sheet for more information.

buffering, and logic level translation for 3 V or 5 V digital signals. Clock Connectors

Documentation for the AD9802-EB is included, consisting of a

board description, schematic and layout information.

J10 CLPDM

J11 SHD

J12 SHP

J13 CLPOB

J14 PBLK

J15 ADCCLK

All of the clock inputs are 50 Ω terminated and buffered by an

LVXC3245 transceiver. The supply level at J7 determines the

input clock level compatibility. The outputs of the LVXC3245

always send +3 V clock levels to the AD9801/AD9802.

–12–

REV. 0

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