NCV7380(2004) データシートの表示（PDF） - ON Semiconductor

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NCV7380
(Rev.:2004)

LIN Transceiver

ON Semiconductor 

NCV7380

ELECTRICAL CHARACTERISTICS (continued) (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.)

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

TXD

High Level Input Voltage

Low Level Input Voltage

TxD Pull Up Resistor

RXD

Low Level Output Voltage

Leakage Current

AC CHARACTERISTICS

Vih

Vil

RIH_TXD

Rising Edge

Falling Edge

VTxD = 0 V

Vol_rxd

Vleak_rxd

IRxD = 2.0 mA

VRxD = 5.5 V, Recessive

−

−

0.7*VCC

V

0.3*VCC

−

−

V

10

15

20

kW

−

−

−1.0

−

0.9

V

1.0

mA

Propagation Delay Transmitter

(Notes 9 and 11)

ttrans_pdf

Bus Loads: 1.0 KW/1.0 nF,

−

−

ttrans_pdr

660 W/6.8 nF, 500 W/10 nF

Propagation Delay Transmitter Symmetry ttrans_sym Calculate ttrans_pdf − ttrans_pdr

−2.0

−

(Notes 7 and 11)

5.0

ms

2.0

ms

Propagation Delay Receiver

(Notes 7, 8, 9, 11 and 14)

trec_pdf

trec_pdr

CRxD = 20 pF

−

−

Propagation Delay Receiver Symmetry

trec_sym

Calculate ttrans_pdf − ttrans_pdr

−1.5

−

(Notes 7 and 8)

6.0

ms

1.5

ms

Slew Rate Rising and Falling Edge,

High Battery (Notes 7 and 12)

tSR_HB

Bus Loads: VS = 18 V,

1.0

2.0

3.0

V/ms

1.0 KW/1.0 nF, 660 W/6.8 nF,

500 W/10 nF

Slew Rate Rising and Falling Edge,

Low Battery (Notes 7 and 12)

tSR_LB

Bus Loads: VS = 7.0 V,

0.5

2.0

3.0

V/ms

1.0 KW/1.0 nF, 660 W/6.8 nF,

500 W/10 nF

Slope Symmetry, High Battery

(Notes 7 and 12)

Bus Duty Cycle (Notes 8 and 15)

Receiver Debounce Time

(Notes 10, 13 and 14)

tssym_HB

Bus Loads: VS = 18 V,

−5.0

−

1.0 KW/1.0 nF, 660 W/6.8 nF,

500 W/10 nF, Calculate

tsdom−tsrec

5.0

ms

D1

Calculate tBUS_rec(min)/100 ms

0.396

−

−

ms/ms

D2

Calculate tBUS_rec(max)/100 ms

−

−

0.581 ms/ms

trec_deb

BUS Rising and Falling Edge

1.5

−

4.0

ms

7. In accordance to LIN physical layer specification 1.3.

8. In accordance to LIN physical layer specification 2.0.

9. Propagation delays are not relevant for LIN protocol transmission, only symmetry.

10. No production test, guaranteed by design and qualification.

11. See Figure 2 − Input/Output Timing.

12. See Figure 7 − Slope Time Calculation.

13. See Figure 3 − Receiver Debouncing.

14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ms.

15. See Figure 8 − Duty Cycle Measurement and Calculation.

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