NTE6508 データシートの表示（PDF） - NTE Electronics
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NTE6508 Datasheet PDF : 4 Pages
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DC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Standby Supply Current
Operating Supply Current
Data Retention Supply Current
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Voltage, LOW
Input Voltage, HIGH
Output Voltage, LOW
Output Voltage, HIGH
ICC(SB)
ICC(OP)
ICC(DR)
VCC(DR)
II
IOZ
VIL
VIH
VOL
VOH
IO = 0, VI = VCC or GND, VCC = 5V
E = 1MHz, IO = 0, VI = VCC or GND,
VCC = 5.5V, Note 2
VCC = 2V, IO = 0, VI = VCC or GND,
E = VCC
VI = VCC or GND, VCC = 5.5V
VO = VCC or GND, VCC = 5.5V
VCC = 4.5V
VCC = 5.5V
IO = 3.2mA, VCC = 4.5V
IO = –0.4mA, VCC = 4.5V
–
–
–
2.0
–1.0
–1.0
–0.3
VCC–2
–
2.4
–
10
µA
–
4
mA
–
10
µA
–
–
V
– +1.0 µA
– +1.0 µA
– +0.8 V
– VCC+0.3 V
–
0.4
V
–
–
V
Note 2. Typical derating 1.5mA/MHz increase in ICC(OP).
Capacitance: (TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Capacitance
Output Capacitance
CI f = 1MHz, All measurements are ref- –
CO erenced to device GND
–
–
6 pF
– 10 pF
AC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Chip Enable Access Time
TELQV Note 3, Note 5
–
– 300 ns
Address Access Time
TAVQV Note 3, Note 5, & Note 6
–
– 300 ns
Chip Enable Output Enable Time
TELQX Note 4, Note 5
5
– 160 ns
Write Enable Output Disable Time
TWLQZ Note 4, Note 5
–
– 160 ns
Chip Enable Output Disable Time
TEHQZ Note 4, Note 5
–
– 160 ns
Chip Enable Pulse Negative Width
TELEH Note 3, Note 5
300 –
– ns
Chip Enable Pulse Positive Width
TEHEL Note 3, Note 5
100 –
– ns
Address Setup Time
TAVEL Note 3, Note 5
0
–
– ns
Address Hold Time
TELAX Note 3, Note 5
50 –
– ns
Data Setup Time
TDVWH Note 3, Note 5
110 –
– ns
Data Hold Time
TWHDX Note 3, Note 5
0
–
– ns
Chip Enable Write Pulse Setup Time TWLEH Note 3, Note 5
130 –
– ns
Chip Enable Write Pulse Hold Time TELWH Note 3, Note 5
130 –
– ns
Write Enable Pulse Width
TWLWH Note 3, Note 5
130 –
– ns
Read or Write Cycle Time
TELEL Note 3, Note 5
350 –
– ns
Note 3. Input pulse levels: 0.8V to VCC –2V; Input rise and fall times: 5ns (max); Input and output
timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) – for CL
greater than 50pF, access time is derated by 0.15ns per pF.
Note 4. Tested at initial design and after major design changes.
Note 5. VCC = 4.5V and 5.5V.
Note 6. TAVQV = TELQV + TAVEL.
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