ORT8850 データシートの表示（PDF） - Lattice Semiconductor
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ORT8850
Lattice Semiconductor
ORT8850 Datasheet PDF : 105 Pages
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
Table of Contents
Introduction .................................................................. 1
Table of Contents......................................................... 2
Features ....................................................................... 3
Embedded Core Features............................... 3
FPGA Features ............................................... 4
Programmable Logic System Features........... 5
Description ................................................................... 6
What is an FPSC?........................................... 6
FPSC Overview............................................... 6
ispLEVER Development System..................... 7
FPSC Design Kit ............................................. 7
FPGA Logic Overview..................................... 8
System-Level Features ................................... 9
Configuration................................................. 10
Additional Information ................................... 10
ORT8850 Overview ................................................... 11
Embedded Core Overview ............................ 11
SONET Logic Blocks - Overview .................. 12
System Considerations for Reference Clock
Distribution.............................................. 15
SONET Bypass Mode ................................... 16
STM Macrocells - Overview .......................... 17
HSI Macrocell - Overview.............................. 19
Supervisory and Test Support Features - Over-
view ........................................................ 19
Protection Switching - Overview ................... 21
FPSC Configuration - Overview .................... 22
Backplane Transceiver Core Detailed Description .... 25
SONET Logic Blocks, Detailed Description .. 25
Receive Path Logic ....................................... 34
FPGA/Embedded Core Interface Signals .................. 47
Clock and Data Timing at the FPGA/Embedded
Core Interface - SONET Block ............... 49
Powerdown Mode ......................................... 56
Protection Switching...................................... 56
Memory Map .............................................................. 57
Registers Access and General Description... 57
Electrical Characteristics............................................ 69
Absolute Maximum Ratings .......................... 69
Recommended Operating Conditions ........................ 69
Power Supply Decoupling LC Circuit ............ 70
HSI Electrical and Timing Characteristics ..... 71
Embedded Core LVDS I/O............................ 73
Pin Information ........................................................... 77
Package Pinouts ........................................................ 82
Package Thermal Characteristics Summary............ 100
qJA .............................................................. 100
YJC ............................................................. 100
qJC.............................................................. 100
qJB .............................................................. 100
FPSC Maximum Junction Temperature ...... 101
Package Thermal Characteristics ............... 101
Heat Sink Information.................................. 101
Package Coplanarity ................................... 101
Package Parasitics................................................... 102
Package Outline Diagrams ...................................... 102
Terms and Definitions ................................. 102
Package Outline Drawings.......................... 103
Ordering Information ................................................ 104
Revision History ....................................................... 105
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