P90CE201 データシートの表示（PDF） - Philips Electronics

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P90CE201

16-bit microcontroller

Philips Electronics 

Philips Semiconductors

16-bit microcontroller

Product specification

P90CE201

6 SYSTEM CONTROL

6.1 Memory mapping

The P90CE201 accesses the external ROM and RAM via

8 data lines and up to 24 address lines. Data access to or

from the memories is bytewise. The data will be split or

restructured internally to match the internal 16-bit data

format. The upper byte (bits 15 to 8) of the data is taken

from the even address, the lower byte (bits 7 to 0) from the

odd address (MSB address + 1).

For external memory control the device provides the R/WN

signal together with chip enable signals for ROM

(CSROMN) and RAM (CSRAMN). CSROMN is activated

in the internal address range 0H to FFFFFFH. The

CSRAMN signal is activated in the internal address range

1000000H to 1FFFFFFH. In the external world RAM and

ROM are wired in parallel with a maximum address range

of 16 Mbytes each. If the larger memory of RAM or ROM

is smaller than 16 Mbytes the unused address pins can be

used as port pins. The advantages of this addressing

scheme are:

• Maximum flexibility for RAM and ROM sizes.

• The full physical memory size can be used without any

restrictions.

• The minimum number of address pins are used.

The validity of data is signalled to the CPU by the internal

signal DTACKN. This signal is generated internally after a

programmable delay (wait states). By programming the

number of wait cycles the user can adapt the program

execution times to his memory access times. After reset

the delay for the DTACKN signal is set to its maximum

value. Programming the number of wait cycles is

described in section 6.3.2.

handbook, full pagewidth

S0 S1 S2 S3 SB SB S4 S5 S0 S1 S2 S3 SB SB S4 S5 S0 S1

PHI1

A0 A23

D0 D7

R/WN

CSRxMN

(Additional

Wait States)

byte write

byte read

MLB004

August 1993

Fig.10 External memory interface timing - Word access.

17

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