PC85133-1 データシートの表示（PDF） - NXP Semiconductors.

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PC85133-1

Universal LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

25. Figures

Fig 1. Block diagram of PCF85133 . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for PCF85133. . . . . . . . . . . . . . .4

Fig 3. Example of displays suitable for PCF85133 . . . . .5

Fig 4. Typical system configuration . . . . . . . . . . . . . . . . .6

Fig 5. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 6. Static drive mode waveforms . . . . . . . . . . . . . . . .10

Fig 7. Waveforms for the 1:2 multiplex drive mode

with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Fig 8. Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 9. Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 10. Waveforms for the 1:4 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 11. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .17

Fig 12. Relationships between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I2C-bus . . . . . . . . . . . . . . . .18

Fig 13. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 14. Definition of START and STOP conditions. . . . . .25

Fig 15. System configuration . . . . . . . . . . . . . . . . . . . . . .25

Fig 16. Acknowledgement on the I2C-bus . . . . . . . . . . . .26

Fig 17. I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 18. Control byte format . . . . . . . . . . . . . . . . . . . . . . .27

Fig 19. Device protection diagram . . . . . . . . . . . . . . . . . .28

Fig 20. Current consumption with respect to external

clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 21. Driver timing waveforms . . . . . . . . . . . . . . . . . . .34

Fig 22. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .34

Fig 23. Cascaded PCF85133 configuration . . . . . . . . . . .36

Fig 24. Synchronization of the cascade for the various

PCF85133 drive modes . . . . . . . . . . . . . . . . . . . .37

Fig 25. Bare die outline of PCF85133 . . . . . . . . . . . . . . .38

Fig 26. Alignment marks of PCF85133 . . . . . . . . . . . . . .42

Fig 27. Tray details of PCF85133U . . . . . . . . . . . . . . . . .43

Fig 28. Die alignment in the tray . . . . . . . . . . . . . . . . . . .44

PCF85133

Universal LCD driver for low multiplex rates

PCF85133

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 4 July 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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