AT89S8252-33QC データシートの表示（PDF） - Atmel Corporation

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AT89S8252-33QC

8-bit Microcontroller with 8K Bytes Flash

Atmel Corporation 

AT89S8252

UART

The UART in the AT89S8252 operates the same way as

the UART in the AT89C51, AT89C52 and AT89C55. For

further information, see the October 1995 Microcontroller

Data Book, page 2-49, section titled, “Serial Interface.”

Serial Peripheral Interface

The serial peripheral interface (SPI) allows high-speed syn-

chronous data transfer between the AT89S8252 and

peripheral devices or between several AT89S8252

devices. The AT89S8252 SPI features include the

following:

• Full-Duplex, 3-Wire Synchronous Data Transfer

• Master or Slave Operation

• 1.5 MHz Bit Frequency (max.)

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wakeup from Idle Mode (Slave Mode Only)

The interconnection between master and slave CPUs with

SPI is shown in the following figure. The SCK pin is the

clock output in the master mode but is the clock input in the

slave mode. Writing to the SPI data register of the master

CPU starts the SPI clock generator, and the data written

shifts out of the MOSI pin and into the MOSI pin of the

slave CPU. After shifting one byte, the SPI clock generator

stops, setting the end of transmission flag (SPIF). If both

the SPI interrupt enable bit (SPIE) and the serial port inter-

rupt enable bit (ES) are set, an interrupt is requested.

The Slave Select input, SS/P1.4, is set low to select an

individual SPI device as a slave. When SS/P1.4 is set high,

the SPI port is deactivated and the MOSI/P1.5 pin can be

used as an input.

There are four combinations of SCK phase and polarity

with respect to serial data, which are determined by control

bits CPHA and CPOL. The SPI data transfer formats are

shown in Figure 8 and Figure 9.

Figure 7. SPI Master-slave Interconnection

MSB MASTER LSB

8-BIT SHIFT REGISTER

MISO MISO

MSB SLAVE LSB

8-BIT SHIFT REGISTER

MOSI MOSI

SPI

CLOCK GENERATOR

Figure 8. SPI transfer Format with CPHA = 0

SCK SCK

SS

SS

VCC

*Not defined but normally MSB of character just received

15

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