ATMEGA103(1999) データシートの表示（PDF） - Atmel Corporation

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ATMEGA103
(Rev.:1999)

8-bit Microcontroller with 64K/128K Bytes In-System Programmable Flash

Atmel Corporation 

ATmega603/103

The 4096 first Data Memory locations address both the Register file, the I/O Memory and the internal data SRAM. The first

96 locations address the register file and I/O memory, and the next 4000 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega603/103. This SRAM will occupy an area in the remaining

address locations in the 64K address space. This area starts at the address following the internal SRAM. If a 64K external

SRAM is used, 4K of the external memory is lost as the addresses are occupied by internal memory.

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data

SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories

are accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM

operation is enabled by setting the SRE bit in the MCUCR register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means

that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external

SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is

pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte.

This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and

returns will need four clock cycles more than specified in the instruction set manual.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or

Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are decremented and incremented.

The entire data address space including the 32 general purpose working registers and the 64 I/O registers are all accessi-

ble through all these addressing modes. See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The ATmega603/103 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the

program memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different

addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single Register Rd

Figure 8. Direct Single Register Addressing

15

OP

4

0

d

REGISTER FILE

0

d

31

The operand is contained in register d (Rd).

11

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