PE42556 データシートの表示（PDF） - Peregrine Semiconductor Corp.
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PE42556 Datasheet PDF : 10 Pages
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PE42556
Product Specification
Figure 3. Bump Configuration (Bumps Up)
Flip Chip Packaging
Vdd
11
LS
10
GND
9
RF1
8
GND
7
CTRL
12
D-GND
13
DGND
14
RFC
6
Vss
1
D-GND
2
GND
3
RF2
4
GND
5
Table 2. Bump Descriptions
Bump
No.
1
2, 13, 14
3, 5, 7, 9
4
6
8
10
11
12
Bump
Name
VSS
D-GND
GND
RF2
RFC
RF1
LS
VDD
CTRL
Description
Negative supply voltage or GND
connection (Note 3)
Digital Ground
Ground
RF Port 2
RF Common
RF Port 1
Logic Select - Used to determine the
definition for the CTRL pin (see Table 5)
Nominal 3.3V supply connection
CMOS logic level
Note: 3. Use VSS (bump 1, VSS = -VDD) to bypass and disable internal
negative voltage generator. Connect VSS (bump 1) to GND (VSS = 0V) to
enable internal negative voltage generator.
Table 3. Operating Ranges
Parameter
Min Typ Max Units
VDD Positive Power Supply
Voltage
3.0
3.3
3.6
V
VDD Negative Power Supply
Voltage
-3.6
-3.3
-3.0
V
IDD Power Supply Current
(Vss = -3.3V, VDD = 3.0 to
3.6V, -40 to +85 °C)
8.0
12.5
μA
IDD Power Supply Current
(Vss = 0V, VDD = 3.0 to 3.6V,
-40 to +85 °C)
21.5 29.0
μA
ISS Negative Power Supply
Current
(Vss = -3.3V, VDD = 3.0 to
3.6V, -40 to +85 °C)
-18.0 -24.0
μA
Control Voltage High
Control Voltage Low
PIN RF Power In4 (50Ω):
9 kHz ≤ 1 MHz
1 MHz ≤ 13.5 GHz
0.7xVDD
V
0.3xVDD
V
Fig. 4,5 dBm
30
dBm
Note: 4. Please consult Figures 4 and 5 (low-frequency graphs) for recommended
low-frequency operating power level.
Document No. 70-0289-06 │ www.psemi.com
Table 4. Absolute Maximum Ratings
Symbol
VDD
VI
VCTRL
VLS
TST
TOP
PIN5 (50Ω)
VESD
Parameter/Conditions
Power supply voltage
Voltage on any input except
for CTRL and LS inputs
Voltage on CTRL input
Voltage on LS input
Storage temperature range
Operating temperature range
9 kHz ≤ 1 MHz
1 MHz ≤ 13.5 GHz
ESD voltage (HBM)6
ESD voltage (Machine Model)
Min Max Units
-0.3 4.0
V
-0.3
VDD+
0.3
V
4.0
V
4.0
V
-65 150
°C
-40
85
°C
Fig. 4,5 dBm
30 dBm
4000
V
300
V
Notes: 5. Please consult Figures 4 and 5 (low-frequency graphs) for
recommended low-frequency operating power level.
6. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Table 5. Control Logic Truth Table
LS
CTRL
RFC-RF1
0
0
off
0
1
on
1
0
on
1
1
off
RFC-RF2
on
off
off
on
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
Spurious Performance
The typical spurious performance of the PE42556 is
-116 dBm when VSS = 0V (bump 1 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
Switching Frequency
The PE42556 has a maximum 25 kHz switching rate
when the internal negative voltage generator is used
(bump1 = GND). The rate at which the PE42556 can
be switched is only limited to the switching time
(Table 1) if an external negative supply is provided
(bump1 = VSS).
©2009-2012 Peregrine Semiconductor Corp. All rights reserved.
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