DAC-8841FP データシートの表示（PDF） - Analog Devices

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DAC-8841FP

8-Bit Octal, 2-Quadrant Multiplying, CMOS TrimDAC

Analog Devices 

WAFER TEST LIMITS: Vuo = +5 V, All V|hX = +1.5 V, VrefL =0V, =25'C, unless otherwise noted.

Parameter

Symbol

Conditions

DAC-8841GBC

Limits

Units

Integral Nonlinearity

INL

Note 1

±1.5

LSB max

Differential Nonlinearity

DNL

All Devices Monotonic, Note 1

±1

LSB max

Half-Scale Output Voltage

Input Resistance (Vu^jX)

Vhs

PR = 0 V, Sets D = 80h

1.475/1.525

D = 55h; Code Dependent

4

V min/max

kn min

REF Low Resistance

^REpL

D = ABh; Code Dependent

kQ min

DAC Output Voltage Range

OVR

Ri, = 10 kft

V min

DAC Output Current

Slew Rate

Positive

Negative

Positive Supply Current

E DC Power Supply Rejection Ratio

Logic Input High

T Logic Input Low

Logic Input Current

Logic Output High

E Logic Output Low

lorrr

AVqut < 25 mV

Measured 10% to 90%

AVoutX= +3V

^outX = -3 V

PR = OV

^ = 0 V, AVdo = +5%

loH = -0.4 mA

Ir,T = 1.6 mA

mA min

V/jLS min

V/|AS min

mA max

%/% max

V min

V max

fiA max

V min

V max

Electrical tests areperformed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not

guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lotqualifications through sample lotassembly andtesting.

LD3 X 02 X 01 X 00

O DAC REGISTER LOAD.

S qETAIL SERIAL DATA INPUT TIMING

(PR = "1,'V,N = 1.5V,VREFL = t)V)

SOI 1

(DATA IN) 0

B SDO 1

—

O (DATAOUT) 0

—

Vout(FPh)

VqutIOSh)

PRESET TIMING

rs1 LSB ERROR BAND

Figure 1. Timing Diagram

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