PEB20542 データシートの表示（PDF） - Infineon Technologies

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PEB20542

2 Channel Serial Optimized Communication Controller with DMA

Infineon Technologies 

2 Channel Serial Optimized Communication Controller

with DMA

SEROCCO-D

PEB 20542

PEF 20542

Version 1.2

1.1

Features

Serial communication controllers (SCCs)

• Two independent channels

• Full duplex data rates on each channel of up to

16 Mbit/s sync - 2 Mbit/s with DPLL

• 64 Bytes deep receive FIFO per SCC

• 64 Bytes deep transmit FIFO per SCC

P-TQFP-144-10

Serial Interface

• On-chip clock generation or external clock sources

• On-chip DPLLs for clock recovery

• Baud rate generator

• Clock gating signals

• Clock gapping capability

• Programmable time-slot capability for connection to

TDM interfaces (e.g. T1, E1)

• NRZ, NRZI, FM and Manchester data encoding

• Optional data flow control using modem control lines (RTS, CTS, CD)

• Support of bus configuration by collision detection and resolution

Bit Processor Functions

• HDLC/SDLC Protocol Modes

– Automatic flag detection and transmission

– Shared opening and closing flag

– Generation of interframe-time fill ’1’s or flags

– Detection of receive line status

– Zero bit insertion and deletion

CMOS

Type

PEB 20542, PEF 20542

Package

P-TQFP-144-10

Data Sheet

1-19

2000-09-14

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