DMC73CE167 データシートの表示（PDF） - Daewoo Semiconductor
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DMC73CE167 Datasheet PDF : 90 Pages
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29
8Bit Single Chip Microcontroller
DMC73C167
(IOCTL3), and P4 (IOCTL4) of the peripheral file. The individual interrupt mask and resets
are controlled through these registers. The interrupt sources may also be individually
tested by reading the interrupt flags or corresponding input ports. The INTn FLAG values
are independent of the INTn ENABLE values. Writing a 1 to the INTn CLEAR bit will clear
the corresponding INTn FLAG, but writing 0 to the INTn CLEAR bit has no effect on the bit.
For INTn to be recognized by the CPU, three conditions must be met.
1) A 1 must be written to the INTn ENABLE bit in the IOCTL0, IOCTL1, IOCTL3, or IOCTL4
register.
2) The global INTERRUPT ENABLE bit, that is bit 4 in the status register, must be set to 1
by the EINT instruction.
3) INTn must be the highest priority interrupt asserted within an instruction boundary.
Table 5-11. Interrupt Control Registers
Bit
7
R
0
W
P0 0100h IOCTL0 Interrupt Control 0
6
5
4
3
2
0
INT3F INT3E INT2F INT2E
1
INT1F
INT1CLR
0
INT1E
Bit
7
R
W
P0 0101h IOCTL1 Interrupt Control 1
6
5
4
3
2
Not used
INT5F INT5E
1
INT4F
INT4CLR
0
INT4E
Bit
7
R
W
P0 0102h IOCTL2 Interrupt Control 2
6
5
4
3
2
Not used
INT3_0
EDGE
1
INT1
EDGE
0
INT5_0
EDGE
P0 0103h IOCTL3 Interrupt Control 3
Bit
7
6
5
4
3
2
1
0
R INT3_1F INT3_1E INT3_0F INT3_0E INT2_1F INT2_1E INT2_0F INT2_0E
W INT3_1C
INT3_0C
INT2_1C
INT2_0C
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