ISPLSI5384VA-125LB272(2000) データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI5384VA-125LB272
(Rev.:2000)

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5384VA

External Switching Characteristics

Over Recommended Operating Conditions

PARAM.

TEST3

COND.

#

DESCRIPTION 4,5

-125

-100

-70

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

tpd16

A 1 Data Prop. Delay, 5PT Bypass

— 7.5 — 10 — 15 ns

tpd26

A 2 Data Propagation Delay

— 9.5 — 13 — 19 ns

fmax

A 3 Clock Frequency with Internal Feedback1

125 — 100 — 70 — MHz

fmax (Ext.)

— 4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)

91 — 69 — 45 — MHz

fmax (Tog.)

— 5 Clock Frequency, Max Toggle2

167 — 125 — 83 — MHz

tsu1

— 6 GLB Reg. Setup Time before Clk, 5PT bypass

6 — 8 — 12 — ns

tco16

A 7 GLB Reg. Clock to Output Delay

— 4 — 5.5 — 8 ns

th1

— 8 GLB Reg. Hold Time after Clock, 5PT bypass

0 — 0 — 0 — ns

tsu2

— 9 GLB Reg. Setup Time before Clock

7 — 9 — 14 — ns

th2

— 10 GLB Reg. Hold Time after Clock

0 — 0 — 0 — ns

tsu3 (CLK0/1)

—

11

GLB

Path

Reg. Setup

(CLK0/1)

Time

before

Clock,

Input

Reg.

4.5 — 6 — 9 — ns

tsu3 (CLK2/3)

—

12

GLB

Path

Reg. Setup

(CLK2/3)

Time

before

Clock,

Input

Reg.

3.5 — 5 — 7 — ns

th3 (CLK0/1)

—

13

GLB Reg.

(CLK0/1)

Hold

Time

after

Clock,

Input

Reg.

Path

0 — 0 — 0 — ns

th3 (CLK2/3)

—

14

GLB Reg.

(CLK2/3)

Hold

Time

after

Clock,

Input

Reg.

Path

0 — 0 — 0 — ns

tr1

A 15 Ext. Reset Pin to Output Delay

— 15 — 20 — 30 ns

trw1

— 16 Ext. Reset Pulse Duration

7 — 9 — 14 — ns

tptoe/dis

B/C 17 Local Product Term Output Enable/Disable

— 9 — 12 — 18 ns

tgptoe/dis

B/C 18 Global Product Term Output Enable/Disable

— 18 — 24 — 30 ns

tgoe/dis

B/C 19 Global OE Input to Output Enable/Disable

— 6 — 8 — 12 ns

twh

— 20 Ext. Sync. Clock Pulse Duration, High

3 — 4 — 6 — ns

twl

— 21 Ext. Sync. Clock Pulse Duration, Low

3 — 4 — 6 — ns

1. Standard 32-bit counter using GRP feedback.

2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

3. Reference Switching Test Conditions section.

4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, and CLK0.

5. Timing parameters measured using normal active output driver.

6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is

used as I/O voltage reference.

Timing Ext.5384VA/4.0.eps

13

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