ISPLSI5384VA-70LB388 データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI5384VA-70LB388 Datasheet PDF : 31 Pages
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Specifications ispLSI 5384VA
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAM # DESCRIPTION
-125
-100
-70
MIN MAX MIN MAX MIN MAX
I/O Buffer
tidcom
22 Input Pad and Buffer, Combinatorial Input
– 0.7 – 0.9 – 1.4
tidreg
23 Input Pad and Buffer, Registered Input
– 4.7 – 6.6 – 9.7
todcom 24 Output Pad and Buffer, Combinatorial Output
– 1.3 – 1.7 – 2.6
todreg
todz
25 Output Pad and Buffer, Registered Output
26 Output Buffer Enable/Disable
– 1.8 – 2.8 – 4.6
– 1.3 – 1.7 – 2.6
tslf
27 Slew Rate Adder, Fast Slew
–0–0–0
tsls
28 Slew Rate Adder, Slow Slew
– 7.5 – 10 – 15
tslfd
29 Programmable Delay Adder, Fast Slew
– 0.5 – 0.7 – 1
tslsd
30 Programmable Delay Adder, Slow Slew
– 8 – 10.7 – 16
GLB/Macrocell Delay Register
tmbp
31 Macrocell Register/Latch Bypass
–0–0–0
tmlat
32 Macrocell Latch Delay
– 1 – 1.4 – 2
tmco
33 Macrocell Register/Latch Clock to Output
–1–1–1
tmsu
34 Macrocell Register/Latch Setup Time
1 – 1.1 – 1.7 –
tmh
35 Macrocell Register/Latch Hold Time
2.5 – 3.9 – 5.3 –
tmsuce 36 Macrocell Register/Latch CLKEN Setup Time
1 – 1.4 – 2 –
tmhce
37 Macrocell Register/Latch CLKEN Hold Time
1 – 1.4 – 2 –
tmrst
38 Macrocell Register/Latch Set/Reset Time
– 1 – 1.4 – 2
tftog
39 Toggle Flip-Flop Feedback
– 1 – 1.3 – 2
AND Array
tandhs
40 AND Array, High Speed Mode
–3–4–6
tandlp
41 AND Array, Low Power Mode
– 5 – 6.6 – 10
PTSA
t5ptcom 42 5 Product Term Bypass, Combinatorial
– 1 – 1.4 – 2
t5ptreg 43
t5ptxcom 44
5 Product Term Bypass, Registered
5 Product Term XOR, Combinatorial
– 1 – 1.7 – 2.3
– 2.5 – 3.6 – 5
t5ptxreg 45 5 Product Term XOR, Registered
– 1.5 – 2.2 – 3.3
tptsacom 46 Product Term Sharing Array, Combinatorial
– 3 – 4.1 – 6
tptsareg 47 Product Term Sharing Array, Registered
– 2.0 – 2.7 – 4.3
PTSA Controls
tpck
tpcken
48 Product Term Clock Delay
49 Product Term CLKEN Delay
– 0.5 – 0.7 – 1
– 1 – 1.4 – 2
tscken
50 Shared Product Term CLKEN Delay
– 1 – 1.4 – 2
tsck
51 Shared Product Term Clock Delay
– 0.5 – 0.7 – 1
tptsacken 52 Product Term Sharing Array CLKEN Delay
– 2.0 – 2.4 – 4
tsrst
53 Shared Product Term Set/Reset Delay
– 2.5 – 3.4 – 5
tprst
tpoe
54 Product Term Set/Reset Delay
55 Product Term Output Enable/Disable
– 1.5 – 2 – 3
– 2.5 – 3.4 – 5
tgpoe
56 Global PT Output Enable/Disable
– 11.5 – 15.4 – 17
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. Internal Timing Parameters are not tested and are for reference only.
Refer to Timing Model in this data sheet for further details.
Timing Rev 4.0
14
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