ISPLSI5384VA-125LQ208 データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI5384VA-125LQ208

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5384VA

Internal Timing Parameters1

Over Recommended Operating Conditions

PARAM # DESCRIPTION

GRP

-125

-100

-70

MIN MAX MIN MAX MIN MAX

tgrpi

57 GRP Delay from I/O Pad

– 1.5 – 2 – 3

tgrpm

58 GRP Delay from Macrocell

– 1.0 – 1.2 – 1.2

Global Control Delays

tgclk01 59 Global Clock 0 or 1 Delay

– 1.2 – 1.7 – 2.4

tgclk23 60 Global Clock 2 or 3 Delay

– 2.2 – 2.7 – 4.4

tgclken0 61 Global CLKEN 0 Delay

– 1.7 – 2.4 – 3.4

tgclken1 62 Global CLKEN 1 Delay

– 2.7 – 3.4 – 5.4

tgrst

63 Global Set/Reset Delay

– 12.2 – 15.8 – 23.4

tgoe

64 Global OE Delay

– 4.7 – 6.3 – 9.4

ttoe

65 Test OE Delay

– 4.7 – 6.2 – 9.4

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

ns

1. Internal Timing Parameters are not tested and are for reference only.

Refer to Timing Model in this data sheet for further details.

Timing Rev 4.0

ispLSI 5384VA Timing Model

Input

Buffer

I/O

Pad

tid#c2o2m

INPUT

tidreg

#23

GRP

#58 tgrpm

#57 tgrpi

Dedicated

Input Buffers

Input

Pad

#59 tgclk01

#60 tgclk23

#61 tgclken0

#62 tgclken1

#63 tgrst

#64 tgoe

#65 ttoe

GLB/Macrocell

AND Array

#40

tandhs

tandlp

#41

PTSA

#42 t5ptcom

#46 tptsacom

#44 t5ptxcom

#45 t5ptxreg

#47 tptsareg

#43 t5ptreg

#39 tftog

#31 tmbp

#32 tmlat

#34 tmsu

#35 tmh

Register #33 tmco

#37 tmhce

PT Controls

#51 tsck

#48 tpck

#52 tptsacken

#49 tpcken

#50 tscken

#36 tmsuce

#38 tmrst

#53 tsrst

#54 tprst

#55 tpoe

#56 tgpoe

Output

Buffer

Buffer Delays

#24 todcom

#25 todreg

#26 todz

Slew

#30 tslsd

#29 tslfd

#27 tslf

#28 tsls

I/O

Pad

OUTPUT

15

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