AD9708-EB データシートの表示（PDF） - Analog Devices
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AD9708-EB Datasheet PDF : 16 Pages
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AD9708
DYNAMIC SPECIFICATIONS (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Single-Ended Output, IOUTA, 50 ⍀ Doubly
Terminated, unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion Ratio
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 12.51 MHz
fCLOCK = 100 MSPS; fOUT = 5.01 MHz
fCLOCK = 100 MSPS; fOUT = 25.01 MHz
Total Harmonic Distortion
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 12.51 MHz
fCLOCK = 100 MSPS; fOUT = 5.01 MHz
fCLOCK = 100 MSPS; fOUT = 25.01 MHz
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 12.51 MHz
fCLOCK = 100 MSPS; fOUT = 5.01 MHz
fCLOCK = 100 MSPS; fOUT = 25.01 MHz
NOTES
1Measured single ended into 50 Ω load.
Specifications subject to change without notice.
Min
Typ
Max
Units
100
125
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
50
dB
50
dB
48
dB
50
dB
45
dB
–67
dBc
–67
–62
dBc
–59
dBc
–64
dBc
–48
dBc
68
dBc
62
68
dBc
63
dBc
67
dBc
50
dBc
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
Parameter
Min
Typ
Max
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Specifications subject to change without notice.
3.5
5
2.1
3
0
1.3
0
0.9
–10
+10
–10
+10
5
2.0
1.5
3.5
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
REV. B
DB0–DB7
CLOCK
IOUTA
OR
IOUTB
tS
tPD
tH
tLPW
tST
0.1%
0.1%
Figure 1. Timing Diagram
–3–
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