PLS159 データシートの表示（PDF） - Philips Electronics

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PLS159

Programmable logic sequencer (16 × 45 × 12)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic sequencer

(16 × 45 × 12)

Product specification

PLS159A

FUNCTIONAL DIAGRAM

(LOGIC TERMS)

a

b

(CONTROL TERMS)

PB RB PA RA

LB LA D

EA EB

a

OE

a

b

b

Q

Q

C

C

S

X

B

PR

JQ

F

M

(4)

K

CK

M

T31

T0 FC

PR

JQ

(4)

K

CK

CK

F

CLK

LOGIC FUNCTION

Q3 Q2 Q1 Q0

10 1 0

STATE REGISTER

SR PRESENT STATE

A⋅B⋅C⋅...

0 0 0 1 Sn + 1 NEXT STATE

⋅ SET Q0: J0 = (Q3 Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

K0 = 0

RESET

Q1:

J1

K1

=

=

0

(Q3⋅

Q2

⋅

Q1

⋅

Q0)

⋅

A

⋅

B

⋅

C

.

.

.

HOLD Q2: J2 = 0

K2 = 0

TOGGLE Q3: J3 = (Q3 ⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

K3 = (Q3⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

NOTE:

Similar logic functions are applicable for D

and T mode flip-flops.

FLIP-FLOP TRUTH TABLE

OE L CK P R J K Q F

H

Hi-Z

L X X L XX XL H

L X X H LX XH L

L X X L HX XL H

L L ↑ L L L LQ Q

L L ↑ L LL HL H

L L ↑ L LH LH L

L L ↑ L L H HQ Q

H H ↑ L L L H L H*

H H ↑ L L H L H L*

+10V X ↑ X X L H L H* *

X ↑ X X H L H L* *

NOTES:

1. Positive Logic:

J-K = T0 + T1 + T2 ……………… T31

Tn = C⋅ (I0 ⋅ I1 ⋅ I2 …) ⋅ (Q0 ⋅ Q1 …) ⋅

(B0 ⋅ B1 ⋅ …)

2. ↑ denotes transition from Low to High level.

3. X = Don’t care

4. * = Forced at Fn pin for loading the J-K

flip-flop in the Input mode. The load

control term, Ln must be enabled (HIGH)

and the p-terms that are connected to the

associated flip-flop must be forced LOW

(disabled) during Preload.

5. At P = R = H, Q = H. The final state of Q

depends on which is released first.

6. * * = Forced at Fn pin to load J-K flip-flop

independent of program code (Diagnostic

mode), 3-State B outputs.

October 22, 1993

27

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