PLUS405-55A データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

PLUS405-55A

Programmable logic sequencer (16 × 64 × 8)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic sequencer

(16 × 64 × 8)

Product specification

PLUS405-55

TIMING DEFINITIONS

SYMBOL

tCKH1, 2

tCKP1, 2

PARAMETER

Width of input clock pulse.

Minimum guaranteed clock

period.

tIS1

Required delay between

beginning of valid input and

positive transition of Clock.

tCKO1, 2

Delay between positive

transition of Clock and when

Outputs become valid (with

INIT/OE Low).

tPPR

Delay between VCC (after

power-on) and when Outputs

become preset at “1”.

tIS2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through

the AND Array).

tRJH

Required delay between

positive transition of clock,

and return of input I10, I11 or

I12 from Diagnostic Mode

(10V).

fMAX1, 2 Minimum guaranteed

operating frequency; input to

output (CLK1 and CLK2).

fMAX3, 4

Minimum guaranteed

operating frequency; input

through Complement Array,

to output (CLK1 and CLK2).

fMAX5

Minimum guaranteed internal

operating frequency; with

internal feedback from state

register to state register.

SYMBOL

fMAX6

PARAMETER

Minimum guaranteed internal

operating frequency with

Complement Array, with

internal feedback from state

register through Complement

Array, to state register.

fCLK

Minimum guaranteed clock

frequency (register toggle

frequency).

tCKL1, 2 Interval between clock

pulses.

tIH

Required delay between

positive transition of Clock

and end of valid Input data.

tOE

Delay between beginning of

Output Enable Low and when

Outputs become valid.

tSRE

Delay between input I12

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tRJS

Required delay between

inputs I11, I10 or I12

transition to Diagnostic Mode

(10V), and when the output

pins become available as

inputs.

tNVCK

Required delay between the

negative transition of the

clock and the negative

transition of the

Asynchronous Initialization to

guarantee that the clock edge

is not detected as a valid

negative transition.

SYMBOL

PARAMETER

tINITH

Width of initialization input

pulse.

tVS

Required delay between VCC

(after power-on) and negative

transition of Clock preceding

first reliable clock pulse.

tOD

Delay between beginning of

Output Enable High and

when Outputs are in the

OFF-state.

tINIT

Delay between positive

transition of Initialization and

when Outputs become valid.

tSRD

Delay between input I12

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

tRH

Required delay between

positive transition of Clock

and end of valid Input data

when jamming data into State

or Output Registers in

diagnostic mode.

tVCK

Required delay between

negative transition of

Asynchronous Initialization

and negative transition of

Clock preceding first reliable

clock pulse.

October 22, 1993

191

Share Link: