TE28F008BE-B120 データシートの表示（PDF） - Intel
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TE28F008BE-B120 Datasheet PDF : 58 Pages
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E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
4.7 AC Characteristics— CE#–Controlled Write Operations(1, 12)—Commercial
(Continued)
Sym
Parameter
Prod
VCC
Load
Note
BV-120
3.3 ± 0.3 V(9) 5 V ± 10%(11)
50 pF
100 pF
Min Max Min Max
Unit
tAVAV Write Cycle Time
180
120
ns
tPHEL RP# High Recovery to CE# Going Low
1.5
0.45
µs
tWLEL WE# Setup to CE# Going Low
0
0
ns
tPHHEH Boot Block Lock Setup to CE# Going
6,8
200
100
ns
High
tVPEH VPP Setup to CE# Going High
5,8
200
100
ns
tAVEH Address Setup to CE# Going High
3
150
50
ns
tDVEH Data Setup to CE# Going High
4
150
50
ns
tELEH
CE# Pulse Width
150
50
ns
tEHDX Data Hold Time from CE# High
4
0
0
ns
tEHAX Address Hold Time from CE# High
3
0
0
ns
tEHWH WE # Hold Time from CE# High
0
0
ns
tEHEL CE# Pulse Width High
30
30
ns
tEHQV1 Duration of Word/Byte Programming
2,5
6
6
µs
Operation
tEHQV2 Duration of Erase Operation (Boot)
2,5,6 0.3
0.3
s
tEHQV3 Duration of Erase Operation (Parameter) 2,5
0.3
0.3
s
tEHQV4 Duration of Erase Operation (Main)
2,5
0.6
0.6
s
tQVVL
VPP Hold from Valid SRD
5,8
0
0
ns
tQVPH RP# VHH Hold from Valid SRD
6,8
0
0
ns
tPHBR Boot-Block Lock Delay
7,8
200
100
ms
NOTES:
See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 11.
12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
SEE NEW DESIGN RECOMMENDATIONS
41
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