ST9294 データシートの表示（PDF） - STMicroelectronics
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ST9294 Datasheet PDF : 6 Pages
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ST9294
1.1 GENERAL DESCRIPTION
The ST9294 is a ROM member of the ST9 family of
microcontrollers, completely developed and pro-
duced by SGS-THOMSON Microelectronics using
a proprietary n-well HCMOS process.
The ROM parts are fully compatible with their
EPROM versions, which may be used for the pro-
totyping and pre-production phases of develop-
ment.
The nucleus of the ST9294 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16-bit Timer/Watchdog with 8-
bit Prescaler, a Serial Peripheral Interface support-
ing S-bus, I2C-bus and IM-bus Interface, plus two
8-bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipe-
lining to add to the efficiency of the code execution
speed of the extensive instruction set.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the ST9294
with up to 31/42 I/O lines dedicated to digital In-
put/Output. These lines are grouped into up to six
I/O Ports and can be configured on a bit basis un-
der software control to provide timing, status sig-
nals, timer inputs and outputs, analog inputs, ex-
ternal interrupts and serial or parallel I/O.
Three basic memory spaces are available to sup-
port this wide range of configurations: Program
Memory, Data Memory and the Register File,
which includes the control and status registers of
the on-chip peripherals.
The 16-bit Slice Timer with an 8-bit Prescaler.
The human interface is provided by the On Screen
Display module, this can produce up to 15 lines of
up to 34 characters from a ROM defined 128 char-
acter set. The 9x13 character can be modified by 4
different pixel sizes, with character rounding, and
formed into words with colour and format attrib-
utes.
Closed Caption control for the display of informa-
tion transmitted through the video input is facili-
tated with the Data Slicer. This module has manual
and automatic Slicing levels for both Sync and
Data and allows the user to select the video line
containing the data relative to the Vertical synchro-
nisation pulse.
Figure 1-2. ST9294 Block Diagram
12k / 24k Bytes
ROM
384 / 640 Bytes
RAM
256 Bytes
REGISTER FILE
16-Bit TIMER / WATCHDOG + SPI
CPU
SLICE
TIMER
MEMORY BUS ( Address & Data )
REGISTER BUS ( Address & Data )
DATA
SLICER
CC Video
I/O PORT 0
8
Note : 42 SDIP shown
I/O PORT 2
( Analog Inputs )
A/D
CONVERTER
I/O PORT 3
ON SCREEN
DISP LAY
I/O PORT 4
P. W. M.
Outputs
6
7
PLL
8
VSYNC HSYNC
AVD D
PLLR
PLLF
P.W.M.
D/A
CONVERTER
I/O PORT 5
( SPI )
2
VR0A1749
3/6
®
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