PSD9342V10JIT データシートの表示（PDF） - STMicroelectronics

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PSD9342V10JIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

INSTRUCTIONS

An instruction consists of a sequence of specific

operations. Each received byte is sequentially de-

coded by the PSD and not executed as a standard

Write operation. The instruction is executed when

the correct number of bytes are properly received

and the time between two consecutive bytes is

shorter than the time-out period. Some instruc-

tions are structured to include Read operations af-

ter the initial Write operations.

The instruction must be followed exactly. Any in-

valid combination of instruction bytes or time-out

between two consecutive bytes while addressing

Flash memory resets the device logic into Read

mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in

Table 7:

Flash memory:

s Erase memory by chip or sector

s Suspend or resume sector erase

s Program a Byte

s Reset to Read mode

s Read primary Flash Identifier value

s Read Sector Protection Status

s Bypass

These instructions are detailed in Table 7. For ef-

ficient decoding of the instructions, the first two

bytes of an instruction are the coded cycles and

are followed by an instruction byte or confirmation

byte. The coded cycles consist of writing the data

AAh to address X555h during the first cycle and

data 55h to address XAAAh during the second cy-

cle. Address signals A15-A12 are Don’t Care dur-

ing the instruction Write cycles. However, the

appropriate Sector Select (FS0-FS7 or

CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have

the same instruction set (except for Read Primary

Flash Identifier). The Sector Select signals deter-

mine which Flash memory is to receive and exe-

cute the instruction. The primary Flash memory is

selected if any one of Sector Select (FS0-FS7) is

High, and the secondary Flash memory is selected

if any one of Sector Select (CSBOOT0-

CSBOOT3) is High.

Power-down Instruction and Power-up Mode

Power-up Mode. The PSD internal logic is reset

upon Power-up to the Read mode. Sector Select

(FS0-FS7 and CSBOOT0-CSBOOT3) must be

held Low, and Write Strobe (WR, CNTL0) High,

during Power-up for maximum security of the data

contents and to remove the possibility of a byte be-

ing written on the first edge of Write Strobe (WR,

CNTL0). Any Write cycle initiation is locked when

VCC is below VLKO.

READ

Under typical conditions, the MCU may read the

primary Flash memory or the secondary Flash

memory using Read operations just as it would a

ROM or RAM device. Alternately, the MCU may

use Read operations to obtain status information

about a Program or Erase cycle that is currently in

progress. Lastly, the MCU may use instructions to

read special data from these memory blocks. The

following sections describe these Read functions.

Read Memory Contents. Primary Flash memory

and secondary Flash memory are placed in the

Read mode after Power-up, chip reset, or a Reset

Flash instruction (see Table 7). The MCU can read

the memory contents of the primary Flash memory

or the secondary Flash memory by using Read op-

erations any time the Read operation is not part of

an instruction.

Read Primary Flash Identifier. The primary

Flash memory identifier is read with an instruction

composed of 4 operations: 3 specific Write opera-

tions and a Read operation (see Table 7). During

the Read operation, address bits A6, A1, and A0

must be 0,0,1, respectively, and the appropriate

Sector Select (FS0-FS7) must be High. The iden-

tifier for the device is E7h.

Read Memory Sector Protection Status. The

primary Flash memory Sector Protection Status is

read with an instruction composed of 4 operations:

3 specific Write operations and a Read operation

(see Table 7). During the Read operation, address

bits A6, A1, and A0 must be 0,1,0, respectively,

while Sector Select (FS0-FS7 or CSBOOT0-

CSBOOT3) designates the Flash memory sector

whose protection has to be verified. The Read op-

eration produces 01h if the Flash memory sector is

protected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks

(primary Flash memory or secondary Flash mem-

ory) can also be read by the MCU accessing the

Flash Protection registers in PSD I/O space. See

the section entitled “Flash Memory Sector Pro-

tect”, on page 22, for register definitions.

Reading the Erase/Program Status Bits. The

PSD provides several status bits to be used by the

MCU to confirm the completion of an Erase or Pro-

gram cycle of Flash memory. These status bits

minimize the time that the MCU spends perform-

ing these tasks and are defined in Table 8. The

status bits can be read as many times as needed.

For Flash memory, the MCU can perform a Read

operation to obtain these status bits while an

Erase or Program instruction is being executed by

the embedded algorithm. See the section entitled

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