QL3060-0PQ208M データシートの表示（PDF） - Unspecified

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QL3060-0PQ208M

PLD Gate pASIC3 FPGA Combining High Performance and High Density

Unspecified 

Military Plastic pASIC 3 Family

Pin Descriptions

Pin

Function

TDI

Test Data In for JTAG

TRSTB

Active low Reset for JTAG

TMS

Test Mode Select for JTAG

TCK

Test Clock for JTAG

TDO

Test data out for JTAG

STM

I/ACLK

I/GCLK

I

I/O

VCC

VCCIO

Special Test Mode

High-drive input and/or

array network driver

High-drive input and/or

global network driver

High-drive input

Input/Output pin

Power supply pin

Input voltage tolerance pin

GND

Ground pin

GND/THERM Ground/Thermal pin

Description

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

Hold LOW during normal operation. Connect to

ground if not used for JTAG.

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

Hold HIGH or LOW during normal operation.

Connect to VCC or ground if not used for JTAG.

Output that must be left unconnected if not used for

JTAG.

Must be grounded during normal operation.

Can be configured as either or both.

Can be configured as either or both.

Use for input signals with high fanout.

Can be configured as an input and/or output.

Connect to 3.3V supply.

Connect to 5.0 volt supply if 5 volt input tolerance is

required, otherwise connect to 3.3V supply.

Connect to ground.

Available on 456-PBGA only. Connect to ground

plane on PCB if heat sinking desired. Otherwise

may be left unconnected.

Ordering Information

QL 3060 –1 PQ208 M

QuickLogic

pASIC device

pASIC 3 device

part number

3012

3025

3040

3060

Speed Grade

0 = quick

1 = fast

2 = faster

Operating Range

M = Military

Package Code

PL84 = 84-pin PLCC

PQ208 = 208-pin PQFP

8-36

36

Preliminary

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