QT1100A-ISG PDF VIEW DOWNLOAD, QT1100A-ISG データシート

QT1100A-ISG データシートの表示（PDF） - Quantum Research Group

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QT1100A-ISG

10 KEY QTOUCH™ SENSOR IC

Quantum Research Group

QT1100A-ISG Datasheet PDF : 42 Pages

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Table 4-1 Serial / EEPROM Setups Block

Data can be sent from the host to the QT1100A in a block of hex data over a serial port. A Setups block received via serial transmission is loaded into RAM (and also into EEPROM

if one is connected). Setups mode is initiated by sending two sequential 0x01 commands to the device. If each byte in the block load sequence is not within 100ms of the preceding

byte, the command will fail and default values or EEPROM values will be used instead of the received Setups block.

EEPROM Setups are a copy of RAM Setups except that EEPROM location 0 will contain 0xD6. Location 0 of the EEPROM must contain 0xD6 or it will not be read. The Setups

block can also be preloaded into EEPROM to control stand-alone (scanport) mode. If the initial 0xD6 is read at power-up, the remainder of the EEPROM is then loaded (provided

the EEPROM CRC is acceptable). EEPROM address location 1 corresponds to Setups block byte 0. If the last EEPROM byte is also fixed at 0xD6 in place of a CRC, EEPROM

CRC checking is disabled.

Note: After any Setups changes, the part should be recalibrated using 0x03 (Enter Cal mode).

Block Byte # Parameter

Neg thresh

0..9 0x00..0x09 Unused

Neg hyst

10..19

0x0A..0x13

Neg drift comp rate

Neg recal delay

20..29

AKS enable

Unused

0x14..0x1D

Error Key

Key To LED

Normal det int limit

0x1E

Pos thresh

Pos hyst

0x1F

Pos drift comp rate

Pos recal delay

Fast (neg) DI Limit

LED Polarity

0x20

Neg Thresh Mode

Sync Enable

Sync pin mode

0x21 Lower BL Limit

0x22 Control bits

0x23 Host CRC

Block length

Sym

NTHR

Unused

NHYS

NDCR

NRD

AKS

Unused

K2L

Byte

Len

NDIL

PTHR

PHYS

PDCR

PRD

FDIL

LEDP

NTM

SYNC

LBLL

KEYO

Unused

HCRC 1

Valid

Range

0..15

0..3

0..15

0, 1

Bits

1..15

2..15

0..15

1..15

0, 1

0..255 8

0, 1

0..7

0..3

Key

Scope

Device

Default

Value

Description

Page

Upper nibble = Neg threshold; 0 = key disabled

Bit_3, 2: Unused

Lower nibble = Neg hysteresis, 3 = 12.5%, 2 = 25%, 1 = 50%, 0 = 0%

7 (2.18s @3ms) Upper nibble = NDCR; 0 = no NDC (via LUT, page 32)

5 (14.42s @3ms) Lower nibble = NRD; 0 = infinite (via LUT, page 34)

0 (disable)

0 (off)

0 (off)*

Bit_7: 1 = AKS enable (each key)

Bit_6: Unused

Bit_5: EK - Key forced active on major error (each key)

Bit_4: 1 = Key to LED function enable (each key)

Note: In Standalone Mode with no EEPROM, K2L = 1 (enabled) on all keys -

Lower nibble = Norm DI Limit; Thresh crossings to detection; min = 1

Upper nibble = Pos threshold; sets sensitivity to +recal

Lower nibble = Pos hysteresis, counts down from +thresh

5 (0.68s @3ms) Upper nibble = PDCR; 0 = no PDC; (via LUT, page 33)

7 (1.03s @3ms) Lower nibble = PRD; (via LUT, page 35)

Upper nibble = Fast Neg DI limit; min = 1

0 (normal) Bit_3: 1 = LED pin is inverted

0 (fixed)

Bit_2: 1 = Ratiometric neg thesh; 0 = fixed thresholds.

0 (off)*

Bit_1: 1 = Sync enabled (default = 0, disabled)

Note: In Standalone Mode with no EEPROM, SYNC = 1 (enabled)

0 (level)

Bit_0: SYNC mode (default = 0, level; 1 = edge)

0x03

Lower limit of acceptable burst length; below this, declares error.

Default = 3 (error on catastrophic channel failure)

0 (disable) Bit_7 = LED pin also shows keypress if KEYO = 1

3 (binary ‘11’) Bit_6,5 = Unused

2 (3ms)

Bit_4,3,2 = Burst spacing (BS), 8 values in increasing order -

2ms, 2.5ms, 3ms, 3.5ms, 4ms, 5ms, 6ms, 7ms settings

1 (9600)

Bit_1,0 = Baud rate (BR); 4 values; UART mode only

4800, 9600 (default), 19.2K, 28.8K in increasing order

CRC of above Setups block (0xD6 disables CRC checking).

See page 41 for algorithm.

Data area is 35 bytes; plus CRC makes 36.

EEPROM area has 37 bytes which also includes an initial 0xD6 byte.

QT1100A-ISG R3.02/1105

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