HIP4080 データシートの表示（PDF） - Intersil

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HIP4080

80V/2.5A Peak, High Frequency Full Bridge FET Driver

Intersil 

HIP4080

VDD

VDD

ENABLE

56K

2N3906

56K

8.2V

100K

100K

0.1µF

FIGURE 32.

VDD RDEL

RDEL

1 BHB

2 HEN

3 DIS

4 VSS

5 OUT

6 IN+

7 IN-

8 HDEL

9 LDEL

10 AHB

BHO 20

BHS 19

BLO 18

BLS 17

VDD 16

VCC 15

ALS 14

ALO 13

AHS 12

AHO 11

VDD

DIS

12V, FINAL VALUE

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

LDEL

t1 =10ms t2

5.1V

NOTES:

2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If

the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+

and IN- pins must cycle at least once.

3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry.

FIGURE 33. TIMING DIAGRAM FOR FIGURE 32

15

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