CY7C4241-10JI データシートの表示（PDF） - Cypress Semiconductor

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CY7C4241-10JI

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

WCLK

tCLKH

WEN1

WEN2

(if applicable)

PAF

RCLK

REN1,

REN2

WCLK

tCLKH

WEN2/LD

WEN1

D0 –D8

Figure 12. Programmable Almost Full Flag Timing

tCLKL

Note

24

tENS tENH

tENS tENH

FULL − M+1 WORDS

IN FIFO

Note

25

tPAF

FULL − M WORDS

IN FIFO[26]

tSKEW2[27]

tENS

tENS tENH

tPAF

Figure 13. Write Programmable Registers

tCLK

tCLKL

tENS

tENS

tENH

tDS

tDH

PAE OFFSET

LSB

PAE OFFSET

MSB

PAF OFFSET

LSB

PAF OFFSET

MSB

Notes

24. If a write is performed on this rising edge of the write clock, there are Full – (m – 1) words of the FIFO when PAF goes LOW.

25. PAF offset = m.

26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,

4096 – m words for CY7C4241, 8192 – m words for CY7C4251.

27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of

RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Document #: 38-06016 Rev. *D

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