RT9206 データシートの表示（PDF） - Richtek Technology

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RT9206

High Efficiency, Synchronous Buck with Dual Linear Controllers

Richtek Technology 

RT9206

The effective series resistance (ESR) of capacitor and

capacitance introduces one zero into system, the zero is

given as :

fZ =

1

2π x rc x CO

(Hz) (22)

In the voltage-mode Buck converter shown in Figure 5, the

loop gain of system is

TL(S) = C(S) x 1 x GP(S) x H(S) = C(S) x G(S) x H(S)

Vr

(23)

The desired loop gain and phase margin is show in the

Bode plot of Figure 8.

G(s)

Gain

VIN/Vr

Power

stage

f

fp

fz

Where the fC is zero crossover frequency defined as the

frequency when the loop gain equals unity. Typically, fC be

chosen in range 1/10 ~ 1/20 of switching frequency. fC

determines how fast the dynamic load response is. The

higher fC with the faster dynamic response, and the phase

margin in the range of 45° ~ 60° is desirable.

So, the transfer function of compensator C(s) must be

designed to meet these requirements. In many applications,

use an electrolytic capacitor as the output capacitor, if the

zero (fZ) caused by effective series resistance (ESR) of

capacitor is a few kHz and smaller than 8 times fP, the

type 2 (PI) can be used to get desired compensation. Figure

9 shows the typical type 2 trans-conductance error

amplifier and the Bode plot is also shown in Figure 10.

VOUT VREF

Ra

+gm

Vc

-

Rc1

Cc2

Rb

Cc1

TL(s)

Desired

loop gain

fc

Figure 9. The typical type 2 trans-conductance error

amplifier.

f

Gain(dB)

Phase

0°

-90 °

-180 °

f

Phase

margin

Figure 8. The Bode plot of desired loop gain and phase

margin

gmRc1

Phase fcz

f

fcp

Boost

-90

f

Figure 10. The Bode plot of type 2 trans-conductance

error amplifier

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18

DS9206-11 March 2007

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