S-24C01A データシートの表示（PDF） - Seiko Instruments Inc

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S-24C01A

CMOS 2-WIRE SERIAL EEPROM

Seiko Instruments Inc 

Rev. 2.2_30

CMOS 2-WIRE SERIAL EEPROM

S-24C01A/02A/04A

7.3 Sequential Read

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in

both current and random read operations, following the start condition signal, it outputs the

acknowledgment signal

When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory

address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by

which the 8th data is output.

When the master device transmits the acknowledgment signal, the next memory address data is output.

When the master device transmits the acknowledgment signal, the memory address counter inside the

EEPROM is incremented and read data in succession. This is called "Sequential Read."

When the master device does not output an acknowledgement signal and transmits the stop condition

signal, the read operation is finished.

Data can be read in the "Sequential Read" mode in succession. When the memory address counter

reaches the last word address, it rolls over to the first memory address.

R

E

DEVICE A

ADDRES D

SDA LINE

1 D7

RA

/C

WK

A

C

K

D0 D7

DATA (n)

A

C

K

D0 D7

DATA (n+1)

NO ACK from

Master Device

S

A

T

C

O

K

P

D0 D7

DATA (n+2)

D0

DATA (n+x)

ADR INC

ADR INC

ADR INC

ADR INC

Figure 14 Sequential Read

Seiko Instruments Inc.

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