S1D13503F01A データシートの表示（PDF） - Seiko Epson Corp

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S1D13503F01A

LCD Controller ICs

Seiko Epson Corp 

SPECIFICATIONS

Ta = –20 to 75°C

Signal Symbol

Parameter

VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V

Unit Condition

Min. Max. Min. Max.

EXT φ0 tC Clock period

100

—

125

—

ns

VCE

tW

VCE HIGH-level

pulsewidth

tCE

VCE LOW-level

pulsewidth

tC – 50 — tC – 50 —

ns

2tC – 30 — 2tC – 30 —

ns

tCYW Write cycle time

3tC

—

3tC

—

ns

tAHC

Address hold time from

falling edge of VCE

2tC – 30

—

2tC – 40

—

ns

VA0 to

VA15

tASC

tCA

tAS

Address setup time to

falling edge of VCE

Address hold time from

rising edge of VCE

Address setup time to

falling edge of VWR

tC – 70

0

0

— tC – 110 —

—

0

—

—

0

—

ns

ns CL = 100

pF

ns

tAH2

Address hold time from

rising edge of VWR

10

—

10

—

ns

tWSC

Write setup time to

falling edge of VCE

tC – 80 — tC – 115 —

ns

VWR

tWHC

Write hold time from

falling edge of VCE

2tC – 20 — 2tC – 20 —

ns

tDSC

Data input setup time to

falling edge of VCE

tC – 85

— tC – 125 —

ns

VD0 to

VD7

tDHC

Data input hold time

from falling edge of VCE

2tC – 30

—

2tC – 30

—

ns

tDH2

Data hold time from

rising edge of VWR

5

50

5

50

ns

Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read

from the memory is placed on the bus.

14

EPSON

S1D13305 Series

Technical Manual

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