SAA5233 データシートの表示（PDF） - Philips Electronics

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SAA5233

Dual standard PDC decoder

Philips Electronics 

Philips Semiconductors

Dual standard PDC decoder

Objective specification

SAA5233

Register 01: Interrupt (reset state X00X XXXX)

Register R01 is WRITE only.

Table 9 Register 01.

D7

D6

D5

D4

−

8/30/2 IE

VPS IE

−

D3

D2

D1

D0

−

−

−

−

Table 10 Register 01 bit description.

SYMBOL

BIT

FUNCTION

8/30/2 IE

VPS IE

D6

8/30/2 Interrupt Enable.

This allows the reception of Teletext packet 8/30/2 data to be signalled on the INT pin.

When logic 0 reception of Teletext packet 8/30/2 data is not signalled on INT pin.

When logic 1 reception of Teletext packet 8/30/2 data is signalled on INT pin.

D5

VPS Interrupt Enable.

This allows the reception of VPS data to be signalled on the INT pin.

When logic 0 reception of VPS data is not signalled on INT pin.

When logic 1 reception of VPS data is signalled on INT pin.

Register 02 to 0F (HEX): VPS data bytes

A single VPS data bytes is stored as two memory bytes, the least significant nibble of both memory bytes is the data

making up the single VPS data byte. The most significant nibble of each memory byte is used to indicate a biphase error

in the least significant nibble. This is indicated by the least significant bit being set, the top three bits are not used and

are fixed to logic 0 (see Table 11).

Table 11 VPS data bytes.

ADDRESS (HEX)

02

03

REGISTER

VPS B5 least significant nibble

VPS B5 most significant nibble

Note

1. Equivalent to VPS B5 0101 1100 (MSB to LSB).

DATA

0000 1100(1)

0000 0101(1)

Table 12 Register 02.

D7

D6

−

−

D5

D4

D3

D2

D1

D0

−

BIPHASE DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0

ERROR BIT

Register 11 to 1D (HEX): Teletext packet 8/30/2 data bytes

Data is stored as single bytes. The four least significant bits represent the data. The fifth bit if set indicates a Hamming

error in the stored data. The top three bits of the byte are not used and are fixed to logic 0.

Table 13 Register 11.

D7

D6

−

−

D5

D4

D3

D2

D1

D0

−

HAMMING DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0

ERROR BIT

June 1994

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