XC236X データシートの表示（PDF） - Infineon Technologies

部品番号

コンポーネント説明

メーカー

XC236X

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Infineon Technologies 

XC2365

XC2000 Family Derivatives

Preliminary

Functional Description

3.1

Memory Subsystem and Organization

The memory space of the XC236x is configured in a von Neumann architecture, which

means that all internal and external resources, such as code memory, data memory,

registers and I/O ports, are organized within the same linear address space.

Table 3

XC236x Memory Map

Address Area

Start Loc. End Loc. Area Size1) Notes

IMB register space

FF’FF00H FF’FFFFH 256 Bytes –

Reserved (Access trap) F0’0000H FF’FEFFH <1 Mbyte

Minus IMB reg.

Reserved for EPSRAM E8’8000H EF’FFFFH 480 Kbytes Mirrors EPSRAM

Emulated PSRAM

E8’0000H E8’7FFFH 32 Kbytes Flash timing

Reserved for PSRAM E0’8000H E7’FFFFH 480 Kbytes Mirrors PSRAM

Program SRAM

E0’0000H E0’7FFFH 32 Kbytes Maximum speed

Reserved for pr. mem. C9’0000H DF’FFFFH <1.25 Mbytes –

Program Flash 2

C8’0000H C8’FFFFH 64 Kbytes –

Program Flash 1

Program Flash 0

C4’0000H C7’FFFFH 256 Kbytes –

C0’0000H C3’FFFFH 256 Kbytes 2)

External memory area 40’0000H

Available Ext. IO area3) 20’5800H

BF’FFFFH 8 Mbytes

3F’FFFFH < 2 Mbytes

–

Minus USIC/CAN

USIC registers

20’4000H 20’57FFH 6 Kbytes

Accessed via EBC

MultiCAN registers

20’0000H 20’3FFFH 16 Kbytes Accessed via EBC

External memory area 01’0000H 1F’FFFFH < 2 Mbytes Minus segment 0

SFR area

00’FE00H 00’FFFFH 0.5 Kbyte

–

Dual-Port RAM

00’F600H 00’FDFFH 2 Kbytes

–

Reserved for DPRAM 00’F200H 00’F5FFH 1 Kbyte

–

ESFR area

00’F000H 00’F1FFH 0.5 Kbyte

–

XSFR area

00’E000H 00’EFFFH 4 Kbytes

–

Data SRAM

00’A000H 00’DFFFH 16 Kbytes –

Reserved for DSRAM 00’8000H 00’9FFFH 8 Kbytes

–

External memory area 00’0000H 00’7FFFH 32 Kbytes –

1) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.

2) The uppermost 4-Kbyte sector is reserved for internal use.

3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

Data Sheet

28

V0.1, 2007-06

Draft Version

Share Link: