XC2766X データシートの表示（PDF） - Infineon Technologies
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XC2766X Datasheet PDF : 100 Pages
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XC2766X
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Sample time and conversion time of the XC2766X’s A/D Converters are programmable.
The above timing can be calculated using Table 16.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Table 16 A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
000000B
000001B
000010B
:
111110B
111111B
A/D Converter
Basic Clock fADCI
fSYS
fSYS / 2
fSYS / 3
fSYS / (DIVA+1)
fSYS / 63
fSYS / 64
INPCRx.7-0
(STC)
00H
01H
02H
:
FEH
FFH
Sample Time
tS
tADCI × 2
tADCI × 3
tADCI × 4
tADCI × (STC+2)
tADCI × 256
tADCI × 257
Converter Timing Example:
Assumptions: fSYS
Basic clock
fADCI
Sample time
tS
Conversion 10-bit:
tC10
Conversion 8-bit:
tC8
= 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
= tADCI × 2 = 121 ns
= 17 × tADCI = 17 × 60.6 ns = 1.03 µs
= 15 × tADCI = 15 × 60.6 ns = 0.91 µs
Converter Timing Example:
Assumptions: fSYS
Basic clock
fADCI
Sample time
tS
Conversion 10-bit:
tC10
Conversion 8-bit:
tC8
= 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H
= fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns
= tADCI × 5 = 375 ns
= 20 × tADCI = 20 × 75 ns = 1.5 µs
= 18 × tADCI = 18 × 75 ns = 1.35 µs
Data Sheet
79
V0.1, 2007-09
Draft Version
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