C167CS-4R データシートの表示（PDF） - Infineon Technologies

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C167CS-4R

16-Bit CMOS Single-Chip Microcontrollers C166 Family

Infineon Technologies 

C167CS-4R

C167CS-L

The C167CS also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.

Hardware traps cause immediate non-maskable system reaction which is similar to a

standard interrupt service (branching to a dedicated vector table location). The

occurrence of a hardware trap is additionally signified by an individual bit in the trap flag

register (TFR). Except when another higher prioritized trap service is in progress, a

hardware trap will interrupt any actual program execution. In turn, hardware trap services

can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Vector

Trap

Location Number

Reset Functions:

–

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

RESET

RESET

RESET

00’0000H 00H

00’0000H 00H

00’0000H 00H

Class A Hardware Traps:

– Non-Maskable Interrupt NMI

NMITRAP 00’0008H 02H

– Stack Overflow

STKOF STOTRAP 00’0010H 04H

– Stack Underflow

STKUF STUTRAP 00’0018H 06H

Class B Hardware Traps:

– Undefined Opcode

– Protected Instruction

Fault

UNDOPC BTRAP

PRTFLT BTRAP

00’0028H 0AH

00’0028H 0AH

– Illegal Word Operand ILLOPA BTRAP

Access

00’0028H 0AH

– Illegal Instruction

Access

ILLINA BTRAP 00’0028H 0AH

– Illegal External Bus

Access

ILLBUS BTRAP 00’0028H 0AH

Reserved

–

–

Software Traps

–

–

– TRAP Instruction

[2CH –

3CH]

[0BH –

0FH]

Any

Any

[00’0000H – [00H –

00’01FCH] 7FH]

in steps

of 4H

Trap

Priority

III

III

III

II

II

II

I

I

I

I

I

–

Current

CPU

Priority

Data Sheet

22

V2.2, 2001-08

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