SC508 データシートの表示（PDF） - Semtech Corporation

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SC508

EcoSpeed® DC-DC Buck Controller with Integrated LDO

Semtech Corporation 

SC508/SC508A

Applications Information (continued)

VDDA UVLO and POR

The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib-

its switching and tri-states the DH/DL drivers until VDDA

rises above 3.9V. When VDDA exceeds 3.9V, an internal

POR (Power-On Reset) resets the fault latch and the soft-

start circuitry and then the SC508 is ready to begin a soft-

start cycle. The switcher will shut off if VDDA falls below

3.6V. VDDP does not have UVLO protection.

LDO Regulator

When the LDO is providing bias power to the device, a

minimum 0.1μF capacitor referenced to AGND is required,

along with a minimum 1μF capacitor referenced to PGND

to filter the gate drive pulses. Refer to the PCB Layout

Guidelines section.

Figure 13 shows the ENL voltage thresholds and their

effect on LDO and Switcher operation.

ENL voltage

LDO on

Switcher on if EN = high

1.56V

1.52V

ENL low

threshold

(min 0.4V)

AGND

VIN UVLO hysteresis

LDO on

Switcher off by VIN UVLO

LDO off

Switcher on if EN = high

ENL Pin and VIN UVLO

The ENL pin is also used for the VIN under-voltage lockout

(VIN UVLO) for the switcher. The VIN UVLO voltage is pro-

grammable via a resistor divider at the VIN, ENL and AGND

pins. The VIN UVLO function has a typical threshold of 1.56V

on the VIN rising edge. The falling edge threshold is 1.52V.

Timing is important when driving ENL with logic and not

using the VIN UVLO capability. The ENL pin must transition

from high to low within 2 switching cycles to avoid the

PWM output turning off. If ENL goes below the VIN UVLO

threshold and stays above 1V, then the switcher will turn

off but the LDO will remain on.

Note that it is possible to operate the switcher with the

LDO disabled, but the ENL pin must be below the logic

low threshold (0.4V maximum), otherwise the VIN UVLO

function will disable the switcher.

The next table summarizes the function of the ENL and EN

pins, with respect to the rising edge of ENL.

EN

ENL

LDO status Switcher status

low low, < 0.4V

off

off

high low, < 0.4V

off

on

low high, < 1.52V

on

off

high high, < 1.52V

on

off

low high, > 1.56V

on

off

high high, > 1.56V

on

on

Figure 13 — ENL Thresholds

ENL Logic Control of PWM Operation

When the ENL input exceeds the VIN UVLO threshold of

1.56V, internal logic checks the PGOOD signal. If PGOOD

is high, the switcher is already running and the LDO will

start without affecting the switcher. If PGOOD is low, the

device disables PWM switching until the LDO output has

reached 90% of its final value. This delay prevents the

additional current needed by the DH and DL gate drives

from overloading the LDO at start-up.

LDO Start-up

Before LDO start-up, the device checks the status of the

following signals to ensure proper operation can be

maintained.

1. ENL pin

2. VLDO output

3. VIN input voltage

When the ENL pin is high and VIN voltage is available, the

LDO will begin start-up. During the initial phase when

VLDO is below 1V, the LDO initiates a current-limited start-

up (typically 20mA). This protects the LDO from thermal

damage if the VLDO pin is shorted to ground. As VLDO

exceeds 1V, the start-up current gradually increases to

20

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