SC68C2550B データシートの表示（PDF） - NXP Semiconductors.

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SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode µP interface

NXP Semiconductors. 

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.7 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconfigured for loopback internally

(see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)

are disconnected from their associated interface pins, and instead are connected together

internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal

modem control inputs pins, and instead are connected internally to MCR[1] RTS, MCR[0]

DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the transmit

holding register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

transmit/receive circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational.

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

© NXP B.V. 2009. All rights reserved.

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