SC68C2550B データシートの表示（PDF） - NXP Semiconductors.

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SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode µP interface

NXP Semiconductors. 

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5. Pinning information

5.1 Pinning

D5 1

D6 2

D7 3

RXB 4

RXA 5

TXRDYB 6

TXA 7

TXB 8

OP2B 9

CS 10

A3 11

n.c. 12

SC68C2550BIB48

36 RESET

35 DTRB

34 DTRA

33 RTSA

32 OP2A

31 RXRDYA

30 IRQ

29 n.c.

28 A0

27 A1

26 A2

25 n.c.

002aab335

Fig 2. Pin configuration for LQFP48

5.2 Pin description

Table 2.

Symbol

A0

A1

A2

A3

CDA

CDB

CS

CTSA

CTSB

Pin description

Pin

Type

28

I

27

I

26

I

11

I

40

I

16

I

10

I

38

I

23

I

Description

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

Address 2 select bit. Internal register address selection.

Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects Channel A,

and a logic HIGH selects Channel B. (See Table 3.)

Carrier Detect (active LOW). These inputs are associated with individual UART channels A

through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for

that channel.

Chip Select (active LOW). This pin enables data transfers between the user CPU and the

SC68C2550B for the channel(s) addressed. Individual UART sections (A, B) are addressed

by A3. See Table 3.

Clear to Send (active LOW). These inputs are associated with individual UART channels, A

through B. A logic 0 on the CTSn pin indicates the modem or data set is ready to accept

transmit data from the SC68C2550B. Status can be tested by reading MSR[4]. This pin has

no effect on the UART’s transmit or receive operation.

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

© NXP B.V. 2009. All rights reserved.

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