SC68C2550B データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

メーカー

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode µP interface

NXP Semiconductors. 

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2. Pin description …continued

Symbol Pin

Type Description

RXRDYA 31

RXRDYB 18

O

Receive Ready A, B (active LOW). These outputs provide the receive FIFO/RHR status for

O

individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1

transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to

read/upload, that is, receive ready status with one or more receive characters available in

the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed

trigger level has not been reached. This signal can also be used for single mode transfers

(DMA mode 0).

TXA

7

TXB

8

O

Transmit data A, B. These outputs are associated with individual serial transmit channel

O

data from the SC68C2550B. The TXn pin will be a logic 1 during reset, idle (no data), or

when the transmitter is disabled. During the local Loopback mode, the TXn output pin is

disabled and transmit data is internally connected to the UART receive input.

TXRDYA 43

TXRDYB 6

O

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for

O

individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA

mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB

buffer ready status is indicated by logic 0, that is, at lease one location is empty and

available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no

more empty locations in the FIFO or THR. This signal can also be used for single mode

transfers (DMA mode 0).

VCC

19, 42 I

Power supply input

XTAL1

13

I

Crystal or external clock input. Functions as a crystal input or as an external clock input.

A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit.

Alternatively, an external clock can be connected to this pin to provide custom data rates.

(See Section 6.5 “Programmable baud rate generator”.) See Figure 3.

XTAL2

14

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator

output or buffered clock output. Should be left open if an external clock is connected to

XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ resistor.

n.c.

12, 25, -

not connected

29, 37

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

© NXP B.V. 2009. All rights reserved.

6 of 36

Share Link: